\documentclass[oneside,a4paper]{book} \usepackage{multicol} \begin{document} \title{The Undocumented Z80 Documented} \author{Sean Young} \date{Version 0.4, September 2001} \maketitle \frontmatter \chapter*{Copyright Statement} Copyright \copyright 1997, 1998, 2001 Sean Young.\\ Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled ``GNU Free Documentation License''. \tableofcontents \mainmatter \chapter{Introduction} \section{History} Ever since I first started writing an MSX emulator, I've been very interested in getting the emulation absolutely correct --- including the undocumented features. Not only to make sure that all games work, but also to make sure that if a program crashes, it crashes exactly the same way if running on an emulator as on the real thing. Only then is perfection achieved. I set about collecting information. I found pieces of information on the Internet, but not everything there is to know. So I tried to fill in the gaps, the results of which I put on my website. Various people have helped me since then; this is the result of all those efforts and to my knowledge this document covers more undocumented features than any other. Previous documents I had written were in plain text and Microsoft Word, which I now find very embarrassing, so I decided to combine them all and use {\LaTeX}. Apart from a full re-write, the only changed information is ``Power on defaults'' (section \ref{pon}) and the algorithm for the CF and HF flags for {\tt OTIR} and friends (section \ref{block_io}). \section{Where to get this document} The latest version is always available in {\LaTeX} and pdf at the following location: {\tt http://www.msxnet.org/tech/} \section{Feedback} I welcome any kind of feedback. I would like to hear about any mistakes in this document or any additions you might have. Also note that there are a few flags which are still unknown, I would be most grateful if someone could figure them out (please include an instruction exerciser to show that your findings are correct). You can reach me at {\ttfamily sean@msxnet.org} and my website can be found at {\ttfamily http://www.msxnet.org/}. \chapter{Overview} \section{History of the Z80} In 1969 Intel were approached by a Japanese company called Busicom to produce chips for Busicom's electronic desktop calculator. Intel suggested that the calculator should be built around a single-chip generalized computing engine and thus was born the first microprocessor --- the 4004. Although it was based on ideas from much larger mainframe and mini-computers the 4004 was cut down to fit onto a 16-pin chip, the largest that was available at the time, so that its data bus and address bus were each only 4-bits wide. Intel went on to improve the design and produced the 4040 (an improved 4-bit design) the 8008 (the first 8-bit microprocessor) and then in 1974 the 8080. This last one turned out to be a very useful and popular design and was used in the first home computer, the Altair 8800, and CP/M. In 1975 Federico Faggin who had had worked at Intel on the 4004 and its successors left the company and joined forces with Masatoshi Shima to form Zilog. At their new company Faggin and Shima designed a microprocessor that was compatible with Intel's 8080 (it ran all 78 instructions of the 8080 in exactly the same way that Intel's chip did) but had many more abilities (an extra 120 instructions, many more registers, simplified connection to hardware). Thus was born the mighty Z80! The original Z80 was first released in July 1976. Since then newer versions have appeared with exactly the same architecture but running at higher speeds. The original Z80 ran with a clock rate of 2.5MHz, the Z80A runs at 4MHz, the Z80B at 6MHz, and the Z80H at 8Mhz. Many companies produced machines based around Zilog's improved chip during the 1970's and 80's and because the chip could run 8080 code without needing any changes to the code the perfect choice of operating system was CP/M. \section{Registers} The following accessable registers exist in the Z80. \\[1ex] \begin{tabular}{|c|c|l} \cline{1-2} \tt A & \tt F & Accumlator and Flags \\ \cline{1-2} \cline{1-2} \multicolumn{2}{|c|}{\tt BC} & \\ \cline{1-2} \multicolumn{2}{|c|}{\tt DE} & General purpose registers \\ \cline{1-2} \multicolumn{2}{|c|}{\tt HL} & \\ \cline{1-2} \multicolumn{2}{|c|}{\tt IX} & \\ \cline{1-2} \multicolumn{2}{|c|}{\tt IY} & \raisebox{1.5ex}[0pt]{Index registers} \\ \cline{1-2} \multicolumn{2}{|c|}{\tt PC} & \\ \cline{1-2} \multicolumn{2}{|c|}{\tt SP} & Special purpose registers \\ \cline{1-2} \tt I & \tt R & \\ \cline{1-2} \multicolumn{2}{|c|}{\tt AF'} & \\ \cline{1-2} \multicolumn{2}{|c|}{\tt BC'} & \\ \cline{1-2} \multicolumn{2}{|c|}{\tt DE'} & \raisebox{1.5ex}[0pt]{Alternate general purpose registers}\\ \cline{1-2} \multicolumn{2}{|c|}{\tt HL'} & \\ \cline{1-2} \end{tabular} \\[1ex] For interrupts, there are two interrupt flop-flops, IFF1 and IFF2, and the interrupt mode is remembered. See chapter \ref{interrupts}. Also there is an internal register which is described in section \ref{block_io}. \section{Flags} \label{flags} The conventional way of denoting the flags is with one letter, `C' for the carry flag for example. It could be confused with the C register, so I've chosen to use the `CF' notation for flags. Also in previous things I've written I called the two undocumented flags 5 and 3, but now I've changed to the same notation used in MAME\footnote{http://www.mame.net/}, which is YF and XF, respectively.\\[0.5ex] \begin{tabular}{|l|c|c|c|c|c|c|c|c|} \hline bit & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\ \hline flag & SF & ZF & YF & HF & XF & PF & NF & CF \\ \hline \end{tabular} \begin{description} \item[SF flag] Set if the 2-complement value is negative. It's simply a copy of the most significant bit. \item[ZF flag] Set if the value is zero. \item[YF flag] A copy of bit 5 of the result. \item[HF flag] The half-carry of an addition/subtraction (from bit 3 to 4). Needed for BCD correction with {\tt DAA}. \item[XF flag] A copy of bit 3 of the result. \item[PF flag] This flag can either be the parity of the result (PF), or the \\ 2-compliment signed overflow (VF): set if 2-compliment value doesn't fit in the register. \item[NF flag] Shows whether the last operation was an addition (0) or an subtraction (1). This information is needed for DAA. \item[CF flag] The carry flag, set if there was a carry after the most significant bit. \end{description} \section{Power on defaults} \label{pon} Matt\footnote{redflame@xmission.com} has done some excellent research for this. He found that AF and SP are always set to FFFFh after a reset, and all other registers are undefined (different depending on how long the CPU has been powered off, different for different Z80 chips). Of course the PC should be set to 0 after a reset, and so should the IFF1 and IFF2 flags (otherwise strange things could happen). Also since the Z80 is 8080 compatible, interrupt mode is probably 0. Probably the best way to simulate this in an emulator is set PC, IFF1, IFF2, IM to 0 and set all other registers to FFFFh. \section{Pin Descriptions \cite{datasheet}} This section is also relevant even if you don't do anything with hardware. Besides, it took me hours to draw this picture.\\[1ex] {\tt \setlength{\unitlength}{1mm} \begin{picture}(50,80) \multiput(11.8,2)(0,3.9){20}{\framebox(2,2){}} \multiput(36.2,2)(0,3.9){20}{\framebox(2,2){}} \thicklines \footnotesize \put(14,0){\framebox(22,80){Z80 CPU}} \put(25,80){\oval(3,3)[b]} \thinlines \newcounter{pinno} \multiput(15,76)(0,-3.9){20}{\stepcounter{pinno}\makebox(2,2){\arabic{pinno}}} \multiput(33,2)(0,3.9){20}{\stepcounter{pinno}\makebox(2,2)[r]{\arabic{pinno}}} \put(9,2){\makebox(2,2)[r]{$\mathtt{\overline{IORQ}}$}} \put(9,5.9){\makebox(2,2)[r]{$\mathtt{\overline{MREQ}}$}} \put(9,9.8){\makebox(2,2)[r]{$\mathtt{\overline{HALT}}$}} \put(9,13.7){\makebox(2,2)[r]{$\mathtt{\overline{NMI}}$}} \put(9,17.6){\makebox(2,2)[r]{$\mathtt{\overline{INT}}$}} \put(9,21.5){\makebox(2,2)[r]{$\mathtt{D_1}$}} \put(9,25.4){\makebox(2,2)[r]{$\mathtt{D_0}$}} \put(9,29.3){\makebox(2,2)[r]{$\mathtt{D_7}$}} \put(9,33.2){\makebox(2,2)[r]{$\mathtt{D_2}$}} \put(9,37.1){\makebox(2,2)[r]{$\mathtt{+ 5V}$}} \put(9,41){\makebox(2,2)[r]{$\mathtt{D_6}$}} \put(9,44.9){\makebox(2,2)[r]{$\mathtt{D_5}$}} \put(9,48.8){\makebox(2,2)[r]{$\mathtt{D_3}$}} \put(9,52.7){\makebox(2,2)[r]{$\mathtt{D_4}$}} \put(9,56.6){\makebox(2,2)[r]{$\mathtt{CLK}$}} \put(9,60.5){\makebox(2,2)[r]{$\mathtt{A_{15}}$}} \put(9,64.4){\makebox(2,2)[r]{$\mathtt{A_{14}}$}} \put(9,68.3){\makebox(2,2)[r]{$\mathtt{A_{13}}$}} \put(9,72.2){\makebox(2,2)[r]{$\mathtt{A_{12}}$}} \put(9,76.1){\makebox(2,2)[r]{$\mathtt{A_{11}}$}} \put(39,2){\makebox(2,2)[l]{$\mathtt{\overline{RD}}$}} \put(39,5.9){\makebox(2,2)[l]{$\mathtt{\overline{WR}}$}} \put(39,9.8){\makebox(2,2)[l]{$\mathtt{\overline{BUSACK}}$}} \put(39,13.7){\makebox(2,2)[l]{$\mathtt{\overline{WAIT}}$}} \put(39,17.6){\makebox(2,2)[l]{$\mathtt{\overline{BUSREQ}}$}} \put(39,21.5){\makebox(2,2)[l]{$\mathtt{\overline{RESET}}$}} \put(39,25.4){\makebox(2,2)[l]{$\mathtt{\overline{M1}}$}} \put(39,29.3){\makebox(2,2)[l]{$\mathtt{\overline{RFSH}}$}} \put(39,33.2){\makebox(2,2)[l]{$\mathtt{GND}$}} \put(39,37.1){\makebox(2,2)[l]{$\mathtt{A_0}$}} \put(39,41.0){\makebox(2,2)[l]{$\mathtt{A_1}$}} \put(39,44.9){\makebox(2,2)[l]{$\mathtt{A_2}$}} \put(39,48.8){\makebox(2,2)[l]{$\mathtt{A_3}$}} \put(39,52.7){\makebox(2,2)[l]{$\mathtt{A_4}$}} \put(39,56.6){\makebox(2,2)[l]{$\mathtt{A_5}$}} \put(39,60.5){\makebox(2,2)[l]{$\mathtt{A_{6}}$}} \put(39,64.4){\makebox(2,2)[l]{$\mathtt{A_{7}}$}} \put(39,68.3){\makebox(2,2)[l]{$\mathtt{A_{8}}$}} \put(39,72.2){\makebox(2,2)[l]{$\mathtt{A_{9}}$}} \put(39,76.1){\makebox(2,2)[l]{$\mathtt{A_{10}}$}} \end{picture} } \begin{description} \item[$\mathtt{A_{15}-A_0}$] {\em Address bus} (output, active high, 3-state). This bus is used for accessing the memory and for I/O ports. During the refresh cycle the IR register is put on this bus. \item[$\mathtt{\overline{BUSACK}}$] {\em Bus Acknowledge} (output, active low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals $\mathtt{\overline{MREQ}}$, $\mathtt{\overline{IORQ}}$, $\mathtt{\overline{RD}}$ and $\mathtt{\overline{WR}}$ have been entered into their high-impedance states. The external now control these lines. \item[$\mathtt{\overline{BUSREQ}}$] {\em Bus Request} (input, active low). Bus Request has a higher priority than $\mathtt{\overline{NMI}}$ and is always recognised at the end of the current machine cycle. $\mathtt{\overline{BUSREQ}}$ forces the CPU address bus, data bus and control signals $\mathtt{\overline{MREQ}}$, $\mathtt{\overline{IORQ}}$, $\mathtt{\overline{RD}}$ and $\mathtt{\overline{WR}}$ to go to a high-empedance state so that other devices can control these lines. $\mathtt{\overline{BUSREQ}}$ is normally wired-OR and requres an external pullup for these applications. Extended $\mathtt{\overline{BUSREQ}}$ periods due to extensive DMA operations can prevent the CPU from refreshing dynamic RAMs. \item[$\mathtt{D_7-D_0}$] {\em Data Bus} (input/output, active low, 3-state). Used for data exchanges with memory, I/O and interrupts. \item[$\mathtt{\overline{HALT}}$] {\em Halt State} (output, active low). Indicates that the CPU has executed a {\tt HALT} instruction and is waiting for either a maskable or nonmaskable interrupt (with the mask enabled) before operation can resume. While halted, the CPU stops increasing the PC so the instruction is re-executed, to maintain memory refresh. \item[$\mathtt{\overline{INT}}$] {\em Interrupt Request} (input, active low). Interrupt Request is generated by I/O devices. The CPU honours a request at the end of the current instruction if IFF1 is set. $\mathtt{\overline{INT}}$ is normally wired-OR and requires an external pullup for these applications. \item[$\mathtt{\overline{IORQ}}$] {\em Input/Output Request} (output, active low, 3-state). Indicates that the address bus holds a vailid I/O address for an I/O read or write operation. $\mathtt{\overline{IORQ}}$ is also generated concurrently with $\mathtt{\overline{M1}}$ during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the databus. \item[$\mathtt{\overline{M1}}$] {\em Machine Cycle One} (output, active low). $\mathtt{\overline{M1}}$, together with $\mathtt{\overline{MREQ}}$, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. $\mathtt{\overline{M1}}$, together with $\mathtt{\overline{IORQ}}$, indicates an interrupt acknowledge cycle. \item[$\mathtt{\overline{MREQ}}$] {\em Memory Request} (output, active low, 3-state). Indicates that the address holds a valid address for a memory read or write cycle operations. \item[$\mathtt{\overline{NMI}}$] {\em Non-Maskable Interrupt} (input, negative edge-triggered). $\mathtt{\overline{NMI}}$ has a higher priority than $\mathtt{\overline{INT}}$. $\mathtt{\overline{NMI}}$ is always recognised at the end of the current instruction, independant of the status of the interrupt flip-flops and automatically forces the CPU to restart at location 0066h. \item[$\mathtt{\overline{RD}}$] {\em Read} (output, active low, 3-state). Indicates that the CPU wants to read data from memory or an I/O device. The addressed I/O device or memory should use this signal to place data onto the data bus. \item[$\mathtt{\overline{RESET}}$] {\em Reset} (input, active low). Initializes the CPU as follows: it resets the interrupt flip-flops, clears the PC and IR registes, and set the interrupt mode to 0. During reset time, the address bus and data bus go to a high-empedance state, and all control output signals go to the inactive state. Note that $\mathtt{\overline{RESET}}$ must be active for a minimum of three full clock cycles before the reset operation is complete. Note that Matt found that SP and AF are set to FFFFh. \item[$\mathtt{\overline{RFSH}}$] {\em Refresh} (output, active low). $\mathtt{\overline{RFSH}}$, together with $\mathtt{\overline{MREQ}}$, indicates that the IR registers are on the address bus (note that only the lower 7 bits are useful) and can be used for the refresh of dynamic memories. \item[$\mathtt{\overline{WAIT}}$] {\em Wait} (input, active low). Indicates to the CPU axathat the addressed memory or I/O device are not ready for data transfer,x. The CPU continues to enter a wait state as long as this signal is active. Note that during this period memory is not refreshed. \item[$\mathtt{\overline{WR}}$] {\em Write} (output, active low, 3-state). Indicates that the CPU wants to write data to memory or an I/O device. The addressed I/O device or memory should use this signal to store the data on the data bus. \end{description} \chapter{Undocumented Opcodes} There are quite a few undocumented opcodes/instructions. This section should describe every possible opcode (so you know what will be executed, whatever the value of the opcode is). The following prefixes exist: CB, ED, DD, FD, DDCB and FDCB. Prefixes change the way the following opcodes are interpreted. All instructions without a prefix (not a value of one the above) are single byte opcodes, which are documented in the official documentation. \section{CB Prefix \cite{gerton}} \label{prefix_cb} An opcode with a CB prefix is a rotate, shift or bit test/set/reset instruction. There are a few instructions missing from the official list, which are usually denoted with {\tt SLL} (Shift Logical Left). It works like {\tt SLA}, for one exception: it sets bit 0 ({\tt SLA} resets it). {\tt \begin{tabbing} {\qquad}\=CB30\qquad\=SLL B \+\\ CB31\>SLL C\\ CB32\>SLL D\\ CB33\>SLL E\\ CB34\>SLL H\\ CB35\>SLL L\\ CB36\>SLL (HL)\\ CB37\>SLL A \end{tabbing} } \section{DD Prefix \cite{gerton}} In general, the instruction following the DD prefix is executed as is, but if the HL register is supposed to be used the IX register is used instead. Here are the rules: \begin{itemize} \item Any usage of HL is treated as an access to IX (except {\tt EX DE,HL} and {\tt EXX} and the ED prefixed instructions that use HL). \item Any access to (HL) is changed to (IX+d), where `d' is a signed displacement byte placed after the main opcode --- except {\tt JP (HL)}, which isn't indirect anyway. The mnemonic should be {\tt JP HL}. \item Any access to H is treated as an access to IXh (the high byte of IX) Except if (IX+d) is used as well. \item Any access to L is treated as an access to IXl (the low byte of IX) Except if (IX+d) is used aswell. \item A DD prefix before a CB selects a completely different instruction set, see Section {\ref{prefix_cbdd}}.\\ \end{itemize} Some examples: {\tt \begin{tabbing} {\qquad}\={\rm Without DD prefix}\qquad\={\rm With DD prefix}\+ \\ LD H,(HL)\>LD H,(IX+d)\\ LD H,A\>LD IXh,A\\ LD L,H\>LD IXl,IXh\\ JP (HL)\>JP (IX)\\ LD DE,0\>LD DE,0\\ LD HL,0\>LD IX,0\\ \end{tabbing} } \section{FD Prefix \cite{gerton}} This prefix has the same effect as the DD prefix, though IY is used instead of IX. Note {\tt LD IXl,IYh} is not possible: only IX or IY is accessed in one instruction. \section{ED Prefix \cite{gerton}} There are a number of undocumented EDxx instructions, of which most are duplicates of documented instructions. Any instruction not listed has no effect (same behaviour as 2 {\tt NOP} instructions). The complete list except for the block instructions: \renewcommand{\thefootnote}{\fnsymbol{footnote}} {\footnotetext[7]{Undocumented instruction}} {\tt \begin{tabbing} {\qquad}ED40\quad\=IN B,(C)\qquad\qquad\=ED60\quad\=IN H,(C)\\ {\qquad}ED41\>OUT (C),B\>ED61\>OUT (C),H\\ {\qquad}ED42\>SBC HL,BC\>ED62\>SBC HL,HL\\ {\qquad}ED43\>LD (nn),BC\>ED63\>LD (nn),HL\\ {\qquad}ED44\>NEG\>ED64\>NEG{\footnotemark[7]}\\ {\qquad}ED45 \> RETN\> ED65\> RETN{\footnotemark[7]}\\ {\qquad}ED46\>IM 0\>ED66\>IM 0{\footnotemark[7]}\\ {\qquad}ED47\>LD I,A\>ED67\>RRD\\ {\qquad}ED48\>IN C,(C)\>ED68\>IN L,(C)\\ {\qquad}ED49\>OUT (C),C\>ED69\>OUT (C),L\\ {\qquad}ED4A\>ADC HL,BC\>ED6A\>ADC HL,HL\\ {\qquad}ED4B\>LD BC,(nn)\>ED6B\>LD HL,(nn)\\ {\qquad}ED4C\>NEG{\footnotemark[7]}\>ED6C\>NEG{\footnotemark[7]}\\ {\qquad}ED4D\>RETI\>ED6D\>RETN\footnotemark[7]\\ {\qquad}ED4E\>IM 0{\footnotemark[7]}\>ED6E\>IM 0{\footnotemark[7]}\\ {\qquad}ED4F\>LD R,A\>ED6F\>RLD\\ {\qquad}\\ {\qquad}ED50\>IN D,(C)\>ED70\>IN (C) / IN F,(C){\footnotemark[7]}\\ {\qquad}ED51\>OUT (C),D\>ED71\>OUT (C),0{\footnotemark[7]}\\ {\qquad}ED52\>SBC HL,DE\>ED72\>SBC HL,SP\\ {\qquad}ED53\>LD (nn),DE\>ED73\>LD (nn),SP\\ {\qquad}ED54\>NEG{\footnotemark[7]}\>ED74\>NEG{\footnotemark[7]}\\ {\qquad}ED55\>RETN{\footnotemark[7]}\>ED75\>RETN{\footnotemark[7]}\\ {\qquad}ED56\>IM 1\>ED76\>IM 1{\footnotemark[7]}\\ {\qquad}ED57\>LD A,I\>ED77\>NOP{\footnotemark[7]}\\ {\qquad}ED58\>IN E,(C)\>ED78\>IN A,(C)\\ {\qquad}ED59\>OUT (C),E\>ED79\>OUT (C),A\\ {\qquad}ED5A\>ADC HL,DE\>ED7A\>ADC HL,SP\\ {\qquad}ED5B\>LD DE,(nn)\>ED7B\>LD SP,(nn)\\ {\qquad}ED5C\>NEG{\footnotemark[7]}\>ED7C\>NEG{\footnotemark[7]}\\ {\qquad}ED5D\>RETN{\footnotemark[7]}\>ED7D\>RETN{\footnotemark[7]}\\ {\qquad}ED5E\>IM 2\>ED7E\>IM 2{\footnotemark[7]}\\ {\qquad}ED5F\>LD A,R\>ED7F\>NOP{\footnotemark[7]}\\ \end{tabbing} } \renewcommand{\thefootnote}{\arabic{footnote}} The ED70 instruction reads from I/O port C, but does not store the result. It just affects the flags like the other {\tt IN x,(C)} instruction. ED71 simply outs the value 0 to I/O port C. The ED63 is a duplicate of the 22 opcode ({\tt LD (nn),HL}) and similarly ED6B is a duplicate of the 2A opcode. Of course the timings are different. These instructions are listed in the official documentation. According to Gerton Lunter\footnote{gerton@math.rug.nl}: \begin{quote} The instructions ED 4E and ED 6E are {\tt IM 0} equivalents: when FF was put on the bus (physically) at interrupt time, the Spectrum continued to execute normally, whereas when an EF ({\tt RST 28h}) was put on the bus it crashed, just as it does in that case when the Z80 is in the official interrupt mode 0. In {\tt IM 1} the Z80 just executes a {\tt RST 38h} (opcode FF) no matter what is on the bus. \end{quote} All the {\tt RETI/RETN} instructions are the same, all like the {\tt RETN} instruction. So they all, including {\tt RETI}, copy IFF2 to IFF1. More information on {\tt RETI} and {\tt RETN} and {\tt IM x} is in section \ref{flipflop}. \section{DDCB Prefix} \label{prefix_cbdd} The undocumented DDCB instructions store the result (if any) of the operation in one of the seven all-purpose registers, which one depends on the lower 3 bits of the last byte of the opcode (not operand, so not the offset). \begin{tabbing} {\qquad}000\quad\=B\\ {\qquad}001\>C\\ {\qquad}010\>D\\ {\qquad}011\>E\\ {\qquad}100\>H\\ {\qquad}101\>L\\ {\qquad}110\>(none: documented opcode)\\ {\qquad}111\>A \end{tabbing} The documented DDCB0106 is {\tt RLC (IX+01h)}. So, clear the lower three bits (DDCB0100) and something is done to register B. The result of the RLC (which is stored in (IX+01h)) is now also stored in register B. Effectively, it does the following: {\tt \begin{tabbing} {\qquad}\=LD B,(IX+01h)\+\\ RLC B\\ LD (IX+01h),B \end{tabbing} } So you get double value for money. The result is stored in B and (IX+01h). The most common notation is: {\tt RLC (IX+01h),B} I've once seen this notation: {\tt \begin{tabbing} {\qquad}\=RLC (IX+01h)\+\\ LD B,(IX+01h) \end{tabbing} } That's not correct: B contains the rotated value, even if (IX+01h) points to ROM. The DDCB SET and RES instructions do the same thing as the shift/rotate instructions: {\tt \begin{tabbing} {\qquad}\=DDCB10C0{\qquad}\=SET 0,(IX+10h),B\+\\ DDCB10C1 \>SET 0,(IX+10h),C\\ DDCB10C2 \>SET 0,(IX+10h),D\\ DDCB10C3 \>SET 0,(IX+10h),E\\ DDCB10C4 \>SET 0,(IX+10h),H\\ DDCB10C5 \>SET 0,(IX+10h),L\\ DDCB10C6 \>SET 0,(IX+10h) {\rm - documented instruction}\\ DDCB10C7 \>SET 0,(IX+10h),A \end{tabbing} } So for example with the last instruction, the value of (IX+10h) with bit 0 set is also stored in register A. The DDCB BIT instructions do not store any value; they merely test a bit. That's why the undocumented DDCB BIT instructions are no different from the official ones: {\tt \begin{tabbing} {\qquad}\=DDCB d 78{\qquad}\=BIT 7,(IX+d)\+\\ DDCB d 79\>BIT 7,(IX+d)\\ DDCB d 7A\>BIT 7,(IX+d)\\ DDCB d 7B\>BIT 7,(IX+d)\\ DDCB d 7C\>BIT 7,(IX+d)\\ DDCB d 7D\>BIT 7,(IX+d)\\ DDCB d 7E\>BIT 7,(IX+d) {\rm - documented instruction}\\ DDCB d 7F\>BIT 7,(IX+d) \end{tabbing} } \section{FDCB Prefixes} Same as for the DDCB prefix, though IY is used instead of IX. \section{Combinations of Prefixes} This part may be of some interest to emulator coders. Here we define what happens if strange sequences of prefixes appear in the instruction cycle of the Z80. If CB or ED is encountered, that byte plus the next make up an instruction. FD or DD should be seen as prefix setting a flag which says ``use IX or IY in stead of HL'', and not an instruction. In a large sequence of DD and FD bytes, it is the last one that counts. Also any other byte (or instruction) resets this flag. \\[0.5ex] {\tt {\qquad}FD DD 00 21 00 10{\qquad}NOP NOP NOP LD HL,1000h} \chapter{Undocumented Instructions} \section{BIT instructions} \label{bit_flags} {\tt BIT n,r} behaves much like {\tt AND r,2{\raisebox{1ex}{n}}} with the result thrown away, and CF flag unaffected. So compare {\tt BIT 7,A} with {\tt AND 80h}: flag YF and XF are reset, SF is set if bit 7 was actually set; ZF is set if the result was 0 (bit was reset), and PF is effectively set if ZF is set (the result of the AND leaves either no bits set (PF reset) or one bit set (PF set). So the rules for the flags are: \begin{description} \item[SF flag] Set if n = 7 and tested bit is set. \item[ZF flag] Set if the tested bit is reset. \item[YF flag] Set if n = 5 and tested bit is set. \item[HF flag] Always set. \item[XF flag] Set if n = 3 and tested bit is set. \item[PF flag] Set just like ZF flag. \item[NF flag] Always reset. \item[CF flag] Unchanged. \end{description} This is were things start to get strange. With the {\tt BIT n,(IX+d)} instructions, the flags behave just like the {\tt BIT n,r} instruction, except for YF and XF. These are not copied from the result but from something completely different, namely bit 5 and 3 of the high byte of IX+d (so IX plus the displacement). Things get more bizarre with the {\tt BIT n,(HL)} instruction. Again, except for YF and XF the flags are the same. YF and XF are copied from some sort of internal register. This register is related to 16 bit additations. Most instructions do not change this register. Unfortunately, I haven't tested all instructions yet, but here is the list so far. \begin{description} \item[{\tt ADD HL,xx}] Use the high byte of HL, ie. H before the addition. \item[{\tt LD r,(IX+d)}] Use high byte of the resulting address IX+d. \item[{\tt JR d}] Use high byte target address of the jump. \item[{LD r,r'}] Doesn't change this register. \end{description} Any help here would be most appreciated! \section{Memory Block Instructions \cite{mrison}} \label{block_mem} The {\tt LDI/LDIR/LDD/LDDR} instructions affect the flags in a strange way. At every iteration, a byte is copied. Take that byte and add the value of register A to it. Call that value n. Now, the flags are: \begin{description} \item[YF flag] A copy of bit 1 of n. \item[HF flag] Always reset. \item[XF flag] A copy of bit 3 of n. \item[PF flag] Set if BC not 0. \item[SF, ZF, CF flags] These flags are unchanged. \end{description} And now for {\tt CPI/CPIR/CPD/CPDR}. This instruction compares a series of bytes in memory to register A. Effectively, it can be said it does {\tt CP (HL)} at every iteration. The result of that compare sets the HF flag, which is important for the next step. Take the value of register A, substract the value of the memory address, and finally substract the value of HF flag, which is set or reset by the hypothetical {\tt CP (HL)}. So, {\tt n = A - (HL) - HF}. \begin{description} \item[SF, ZF, HF flags] Set by the hypothetical {\tt CP (HL)}. \item[YF flag] A copy of bit 1 of n. \item[XF flag] A copy of bit 3 of n. \item[PF flag] Set if BC is not 0. \item[NF flag] Always set. \item[CF flag] Unchanged. \end{description} \section{I/O Block Instructions} \label{block_io} These are the most be bizarre instructions, as far as flags is concerned. The PF flag is still unclear\footnote{Help would be most appreciated.}, and the HF and CF are most strange. The out instructions behave differently than the in instructions, which doesn't make the CPU very symmetrical. First for the {\tt OUTI/OTIR/OUTD/OTDR} instructions. At every iteration, a byte is read from memory and sent to an I/O port. Take that value (call it n), and add register L to it, {\em after} the HL register is increased ({\tt OUTI} and {\tt OTIR}) or decreased ({\tt OUTD} and {\tt OTDR}). If that calculation makes a carry (ie. it's larger than 255), both CF and HF are set. Otherwise CF and HF are reset. \begin{description} \item[SF, ZF, YF, XF flags] Affected by decreasing register B, as in {\tt DEC B}. \item[CF, HF flags] Set if (L + n) $>$ 255. \item[NF flags] A copy of bit 7 of n. \item[PF flag] This flag is a mystery. It seems it is dependant on bits 2,1,0 of register C, bits 2,1,0 of n and register B. \end{description} The {\tt INI/INIR/IND/INDR} instructions are slightly different. The value of CF and HF are computed differently. Call the value that is read from the I/O port n. Take the value of register C, and in the the case of {\tt INIR} and {\tt INI}, increase it by 1 and in the case of {\tt INDR} and {\tt IND}, decrease it by 1. Keep the result 8 bits --- so it will be 0 if n was 255, with {\tt INI}. Now add n to this; if it's larger than 255, set the CF and HF flags. Apart from that, the flags are the same. \section{16 bit I/O ports} Officially the Z80 has an 8 bit I/O port address space. When using the I/O ports, the 16 address lines are used. And in fact, the high 8 bit do actually have some value, so you can use 65536 ports after all. {\tt IN r,(C)}, {\tt OUT (C),r}, and the Block I/O instructions actually place the entire BC register on the address bus. Similary {\tt IN A,(n)} and {\tt OUT (n),A} put A $\times$ 256 + n on the address bus. \section{Block Instructions} The repeated block instructions simply decrease the PC by two so the instruction is simply re-executed. So interrupts can occur during block instructions. So, {\tt LDIR} is simply {\tt LDI} + if BC is not 0, decrease PC by 2. \section{16 Bit Additions} The 16 bit additions are a bit more complicated. 16 bit additions are done in two stages: first the lower bytes are added, then the two higher bytes. The SF, YF, HF, XF flags are affected as by the second (high) 8 bit addition. ZF is set if the whole 16 bit result is 0. \section{DAA Instruction} This instruction is useful when you're using BCD values. After an addition or subtraction, {\tt DAA} corrects the value back to BCD again. Note that it uses the CF flag, so it cannot be used after {\tt INC} and {\tt DEC}. Here is the correction table, copied from the ``Mostek Z80 Programming Manual''. This table is all I know about {\tt DAA} operation. \\ \begin{tabular}{c|c|l|c|l|l|l} NF & CF & high & HF & low & \# added & CF after \\ & & nibble & & nibble & to A & execution \\ \hline 0 & 0 & 0-9 & 0 & 0-9 & 00 & 0 \\ 0 & 0 & 0-8 & 0 & a-f & 06 & 0 \\ 0 & 0 & 0-9 & 1 & 0-3 & 06 & 0 \\ 0 & 0 & a-f & 0 & 0-9 & 60 & 1 \\ 0 & 0 & 9-f & 0 & a-f & 66 & 1 \\ 0 & 0 & a-f & 1 & 0-3 & 66 & 1 \\ 0 & 1 & 0-2 & 0 & 0-9 & 60 & 1 \\ 0 & 1 & 0-2 & 0 & a-f & 66 & 1 \\ 0 & 1 & 0-3 & 1 & 0-3 & 66 & 1 \\ \hline 1 & 0 & 0-9 & 0 & 0-9 & 00 & 0 \\ 1 & 0 & 0-8 & 1 & 6-f & fa & 0 \\ 1 & 1 & 7-f & 0 & 0-9 & a0 & 1 \\ 1 & 1 & 6-f & 1 & 6-f & 9a & 1 \\ \hline \end{tabular} \\[2ex] Emulator builders: this instruction is hard to emulate. The Intel 80x86 equivalents are more or less the same, but differ for some input values. The best way to correctly emulate this instruction is by putting all possible output values (for A and F registers) in a table. The output depends on the following inputs: A register and HF, NF, CF flags. That's 11 bits in total, so the table will have size: 2{\raisebox{1ex}{\footnotesize 11} $\times$ 2 = 4096 bytes, which isn't too bad. \chapter{Interrupts} \label{interrupts} There are two types of interrupts, maskable and non-maskable. The maskable type is ignored if IFF1 is reset. Non-maskable interrupts (NMI) will are always accepted, and they have a higher priority, so if the two are requested at the same time the NMI will be accepted first. For the interrupts, the following things are important: Interrupt Mode (set with the {\ttfamily IM 0, IM 1, IM 2} instructions), the interrupt flip-flops (IFF1 and IFF2), and the I register. When a maskable interrupt is accepted, a external device can put a value on the databus. \section{Non-Maskable Interrupts (NMI)} When a NMI is accepted, IFF1 is reset. At the end of the routine, IFF1 must be restored (so the running program is not affected). That's why IFF2 is there; to keep a copy of IFF1. An NMI is accepted when the NMI pin on the Z80 is made low. The Z80 responds to the {\em change} of the line from +5 to 0 --- so the interrupt line doesn't have a state, it's just a pulse. When this happens, a call is done to address 0066h and IFF1 is reset so the routine isn't bothered by maskable interrupts. The routine should end with an {\ttfamily RETN} (RETurn from Nmi) which is just a usual RET, but also copies IFF2 to IFF1, so the IFFs are the same as before the interrupt. You can check whether interrupts were disabled or not during an NMI by using the {\ttfamily LD A,I} or {\ttfamily LD A,R} instruction. These instructions copy IFF2 to the PF flag. \section{Maskable Interrupts (INT)} If the INT line is low and IFF1 is set, a maskable interrupt is accepted --- whether or not the the last INT routine has finished. That's why you should not enable interrupts during such a routine, and make sure that the device that generated it has put the INT line up again before ending the routine. So unlike NMI interrupts, the interrupt line has a state; it's not a pulse. When an INT is accepted, both IFF1 and IFF2 are cleared, preventing another interrupt from occurring which would end up as an infinite loop (and overflowing the stack). What happens next depends on the Interrupt Mode. A device can place a value on the databus when the interrupt is accepted. Some computer systems do not utilize this feature, and this value ends up being FFh. \begin{description} \item[Interrupt Mode 0] This is the 8080 compatibility mode. The instruction on the bus is executed (usually an {\ttfamily RST \#} instruction, but it can be anything. The I register is not used. \item[Interrupt Mode 1] An RST 38h is executed, no matter what value is put on the bus or what value the I register has. \item[Interrupt Mode 2] A call is made to the address read from memory. What address is read from is calculated as follows: (I register) $\times$ 256 + (value on bus). Of course a word (two bytes) are read, making the a address where the call is made to. In this way, you can have a vector table for interrupts. \end{description} At the end of a maskable interrupt, the interrupts should be enabled again. You can assume that was the state of the IFFs because otherwise the interrupt wasn't accepted. So, an INT routine always ends with an {\ttfamily EI} and a {\ttfamily RET} ({\ttfamily RETI} according to the official documentation, more about that later): {\ttfamily \begin{tabbing} INT:\\ {\qquad}\=.\\ \>.\\ \>.\\ \>EI\\ \>RETI {\rmfamily or} RET \end{tabbing} } Note a fact about {\ttfamily EI}: a maskable interrupt isn't accepted directly after it, so the next opportunity for an interrupt is after the {\ttfamily RETI}. This is very useful; if the INT line is still low, an interrupt is accepted again. If this happens a lot and the interrupt is generated before the {\ttfamily RETI}, the stack could overflow (since the routine would be called again and again). But this property of {\ttfamily EI} prevents this. {\ttfamily DI} is not necessary at the start of the interrupt routine: the interrupt flip-flops are cleared when accepting the interrupt. You can use {\tt RET} instead of {\tt RETI}, depending on the hardware setup. {\tt RETI} is only useful if you have something like a Z80 PIO to support daisy-chaining: queueing interrupts. The PIO can detect that the routine has ended by the opcode of {\tt RETI}, and let another device generate an interrupt. That is why I called all the undocumented EDxx RET instructions {\tt RETN}: All of them operate alike, the only difference of {\tt RETI} is its specific opcode which the Z80 PIO recognises. \section{Things affecting the Interrupt flip-flops} \label{flipflop} All the IFF related things are: \begin{tabbing} Accept NMI{\qquad}\=IFF1{\qquad}\=IFF2{\qquad}\= \kill \>IFF1\>IFF2\>\\ CPU reset\>0\>0\\ {\ttfamily DI}\>0\>0\\ {\ttfamily EI}\>1\>1\\ Accept INT\>0\>0\\ Accept NMI\>0\>-\\ {\ttfamily RETI/N}\>IFF2\>-\>All the EDxx RETI/N instructions\\ {\ttfamily LD A,I/LD A,R}\>-\>-\>Copies IFF2 into PF flag \end{tabbing} If you're working with a Z80 system without NMIs (like the MSX), you can forget all about the two separate IFFs; since a NMI isn't ever generated, the two will always be the same. Some documenation says that when an NMI is accepted, IFF1 is first copied into IFF2 before IFF1 is cleared. If this is true, the state of IFF2 is lost after a nested NMI, which is undesirable. Have tested this in the following way: make sure the Z80 is in {\tt EI} mode, generate an NMI. In the NMI routine, wait for another NMI before executing {\tt RETN}. In the second NMI IFF2 was still set, so IFF1 is {\em not} copied to IFF2 when accepting an NMI. Another interesting fact is this. I was trying to figure out whether the undocumented ED {\tt RET} instructions were {\tt RETN} or {\tt RETI}. I tested this by putting the machine in {\tt EI} mode, wait for an NMI and end with one of the ED {\tt RET} instructions. Then execute a {\tt HALT} instruction. If IFF1 was not restored, the machine would hang but this did not happen with any of the instructions, including the documented {\tt RETI}! Since every INT routine must end with {\ttfamily EI} followed by {\ttfamily RETI} officially, It does not matter that RETI copies IFF2 into IFF1; both are set anyway. \section{HALT instruction} The HALT instruction halts the Z80; it does not increase the PC so that the instruction is re-executed, until a maskable or non-maskable interrupt is accepted. Only then does the Z80 increase the PC again and continues with the next instruction. During the HALT state, the HALT line is set. The PC is increased before the interrupt routine is called. \section{Where interrupts are accepted} During execution of instructions, interrupts won't be accepted. Only {\em between} instructions. This is also true for prefixed instructions. Directly after an EI or DI instruction, interrupts aren't accepted. They're accepted again after the instruction after the EI (RET in the following example). So for example, look at this MSX2 routine that reads a scanline from the keyboard: {\tt \begin{tabbing} {\qquad}\=LD{\qquad}\=C,A\+\\ DI\\ IN\>A,(0AAh)\\ AND\>0F0h\\ ADD\>A,C\\ OUT\>(0AAh),A\\ EI\\ IN\>A,(0A9h)\\ RET \end{tabbing} } You can assume that there never is an interrupt after the {\tt EI}, before the {\tt IN A,(0A9h)} --- which would be a problem because the MSX interrupt routine reads the keyboard too. Using this feature of {\tt EI}, it is possible to check whether it is true that interrupts are never accepted during instructions: \begin{tabbing} {\qquad}\={\tt DI}\+\\ {\em make sure INT is active}\\ {\tt EI}\\ {\em insert instruction to test}\-\\ {\tt INT:}\+\\ {\em store PC where INT was accepted}\\ {\tt RET} \end{tabbing} And yes, for all instructions, including the prefixed ones, interrupts are never accepted during an instruction. Only after the tested instruction. Remember that block instructions simply re-execute themselves (by decreasing the PC with 2) so an interrupt is accepted after each iteration. Another predictable test is this: at the ``insert instruction to test'' insert a large sequence of {\tt EI} instructions. Of course, during execution of the {\tt EI} instructions, no interrupts are accepted. But now for the interesting stuff. ED or CB make up instructions, so interrupts are accepted after them. But DD and FD are prefixes, which only slightly affects the next opcode. If you test a large sequence of DDs or FDs, the same happens as with the {\tt EI} instruction: no interrupts are accepted during the execution of these sequences. This makes sense, if you think of DD and FD as a prefix which set the ``use IX instead of HL'' or ``use IY instead of HL'' flag. If an interrupt was accepted after DD or FD, this flag information would be lost, and: {\tt {\qquad}DD 21 00 00{\qquad}LD IX,0 } could be interpreted as a simple {\tt LD HL,0} if the interrupt was after the last DD. Which never happens, so the implementation is correct. Although I haven't tested this, as I imagine the same holds for NMI interrupts. \chapter{Timing and R register} \section{R register and memory refresh} During every first machine cycle (beginning of an instruction or part of it --- prefixes have their own M1 two), the memory refresh cycle is issued. The whole IR register is put on the address bus, and the RFSH pin is lowered. It unclear whether the Z80 increases the R register before or after putting IR on the bus. The R register is increased at every first machine cycle (M1). Bit 7 of the register is never changed by this; only the lower 7 bits are included in the addition. So bit 7 stays the same, but it can be changed using the {\ttfamily LD R,A} instruction. Instructions without a prefix increase R by one. Instructions with an ED, CB, DD, FD prefix, increase R by two, and so do the DDCBxxxx and FDCBxxxx instructions (weird enough). Just a stray DD or FD increases the R by one. {\tt LD A,R} and {\tt LD R,A} access the R register after it is increased (by the instruction itself). Remember that the block instructions simply decrease the PC with two, so the instructions are re-executed. So LDIR increased R by BC times 2 (note that in the case of BC = 0, R is increased by 10000h times 2, effectively 0). Accepting an maskable or non-maskable interrupt increases the R by one. After a hardware reset, or after power on, the R register is reset to 0. That should cover all there is to say about the R register. It is often used in programs for a random value, which is good but of course not truly random. \section{Undocumented Timings} \begin{enumerate} \item Stray DD or FD: same as a NOP (increases R by one). \item EDxx (not one of the list above or block instruction): Same as two NOPs. Increases R by 2. \item Accepting interrupts (all one M1 and thus increase R by one): (T states) IM 0: 13 (assuming the instruction is a RST)\\ IM 1: 13\\ IM 2: 19\\ NMI : 11\\ \end{enumerate} \chapter{Other Information} \section{Errors in official documentation} In some official Zilog documentation, the are some errors. Some don't have all of these mistakes, so your documentation may not be flawed but these are just things to look out for. \begin{itemize} \item The Flag affection summary table shows that {\ttfamily LDI/LDIR/LDD/LDDR} instructions leave the SF and ZF in an undefined state. This is not correct; the SF and ZF flags are unaffected (like the same documentation says). \item Similary, the same table shows that {\ttfamily CPI/CPIR/CPD/CPDR} leave the SF and HF flags in an undefined state. Not true, they are affected as defined elsewhere in the documentation. \item Also, the table says about {\ttfamily INI/OUTD/}etc ``Z=0 if B $<>$ 0 otherwise Z=0''; of course the latter should be Z=1. \item The {\ttfamily INI/INIR/IND/INDR/OUTI/OUTD/OTIR/OTDR} instructions do affect\\ the CF flag (some official documentation says they leave it unaffected, important!) and the NF flag isn't always set but may also be reset (see above for exact operation). \item When an NMI is accepted, the IFF1 isn't copied to IFF2. Only IFF1 is reset. \item In the 8-bit Load Group, the last two bits of the second byte of the {\ttfamily LD r,(IX + d)} opcode should be 10 and not 01. \item In the 16-bit Arithmetic Group, bit 6 of the second byte of the {\ttfamily ADD IX, pp} opcode should be 0, not 1. \item {\ttfamily IN x,(C)} resets the HF flag, it never sets it. Some documentation states it is set according to the result of the operation; this is impossible since no arithmetic is done in this instruction. \end{itemize} \begin{thebibliography}{} \bibitem{mrison} Mark Rison Z80 page for !CPC. \\ {\tt \small http://www.acorn.co.uk/~mrison/en/cpc/tech.html} \bibitem{yaze} YAZE (Yet Another Z80 Emulator). This is a CPM emulator by Frank Cringle. It emulates almost every undocumented flag, very good emulator. Also includes a very good instruction exerciser, and is released under the GPL. \\ {\tt \small ftp://ftp.ping.de/pub/misc/emulators/yaze-1.10.tar.gz} \bibitem{thomas} Z80 Family Official Support Page by Thomas Scherrer. Very good -- your one-stop Z80 page. \\ {\tt \small http://www.geocities.com/SiliconValley/Peaks/3938/z80\_home.htm} \bibitem{speccy_faq} Spectrum FAQ technical information. \\ {\tt \small http://www.void.jump.org/faq/tech\_z80.html} \bibitem{gerton} Gerton Lunter's Spectrum emulator (Z80). In the package there is a file TECHINFO.DOC, which contains a lot of interesting information. Note that the current version can only be unpacked in Windows. \\ {\tt \small ftp://ftp.void.jump.org/pub/sinclair/emulators/pc/dos/z80-400.zip} \bibitem{mostek} Mostek Z80 Programming Manual -- a very good reference to the Z80. \bibitem{datasheet} Z80 Product Specification, from MSX2 Hardware Information. \\ {\tt \small http://www.hardwareinfo.msx2.com/pdf/Zilog/z80.pdf} \end{thebibliography} \chapter{Instruction Tables} \section{8-Bit Load Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline LD r,r' & r$\leftarrow$r' & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 01 & r & r' & & 1 & 1 & 4 & r,r' & Reg\\ \cline{18-19} LD p,p' & p$\leftarrow$p' & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 2 & 2 & 8 & 000 & B \\ \multicolumn{10}{c}{} & 01 & p & p' & \multicolumn{4}{c}{} & 001 & C \\ LD q,q' & q$\leftarrow$q' & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 2 & 2 & 8 & 010 & D \\ \multicolumn{10}{c}{} & 01 & q & q' & \multicolumn{4}{c}{} & 011 & E \\ LD r,n & r$\leftarrow$n & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & r & 110 & & 2 & 2 & 7 & 100 & H \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 101 & L \\ LD p,n & p$\leftarrow$n & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 3 & 3 & 11 & 111 & A \\ \multicolumn{10}{c}{} & 00 & p & 110 & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD q,n & q$\leftarrow$n & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 3 & 3 & 11 & p,p' & Reg \\ \cline{18-19} \multicolumn{10}{c}{} & 00 & q & 110 & \multicolumn{4}{c}{} & 000 & B \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 001 & C\\ LD r,(HL) & r$\leftarrow$(HL) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 01 & r & 110 & & 1 & 2 & 7 & 010 & D \\ LD r,(IX+d) & r$\leftarrow$(IX+d) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 3 & 5 & 19 & 011 & E \\ \multicolumn{10}{c}{} & 01 & r & 110 & \multicolumn{4}{c}{} & 100 & IXh \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & 101 & IXh\\ LD r,(IY+d) & r$\leftarrow$(IY+d) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 3 & 5 & 19 & 111 & A \\ \multicolumn{10}{c}{} & 01 & r & 110 & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD (HL),r & (HL)$\leftarrow$r & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 01 & 110 & r & & 1 & 2 & 7 & q,q' & Reg \\ \cline{18-19} LD (IX+d),r & (IX+d)$\leftarrow$r & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 3 & 5 & 19 & 000 & B \\ \multicolumn{10}{c}{} & 01 & 110 & r & \multicolumn{4}{c}{} & 001 & C \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & 010 & D \\ LD (IY+d),r & (IY+d)$\leftarrow$r & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 3 & 5 & 19 & 011 & E \\ \multicolumn{10}{c}{} & 01 & 110 & r & \multicolumn{4}{c}{} & 100 & IYl \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & 101 & IYh \\ LD (HL),n & (HL)$\leftarrow$n & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 110 & 110 & 36 & 2 & 3 & 10 & 111 & A \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD (IX+d),n & (IX+d)$\leftarrow$n & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 4 & 5 & 19 & & \\ \multicolumn{10}{c}{} & 01 & 110 & 110 & 36 & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD (IY+d),n & (IY+d)$\leftarrow$n & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 4 & 5 & 19 & & \\ \multicolumn{10}{c}{} & 01 & 110 & 110 & 36 & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD A,(BC) & A$\leftarrow$(BC) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 001 & 010 & 0A & 1 & 2 & 7 & & \\ LD A,(DE) & A$\leftarrow$(DE) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 011 & 010 & 1A & 1 & 2 & 7 & & \\ LD A,(nn) & A$\leftarrow$(nn) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 111 & 010 & 3A & 3 & 4 & 13 & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \hline \end{tabular} } (continued)\\ {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline LD (BC),A & (BC)$\leftarrow$A & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 000 & 010 & 02 & 1 & 2 & 7 & & \\ LD (DE),A & (DE)$\leftarrow$A & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 010 & 010 & 12 & 1 & 2 & 7 & & \\ LD (nn),A & (nn)$\leftarrow$A & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 110 & 010 & 32 & 3 & 4 & 13 & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD A,I & A$\leftarrow$I & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & IFF2 & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 2 & 9 & & \\ \multicolumn{10}{c}{} & 01 & 010 & 111 & 57 & \multicolumn{3}{c}{} & & \\ LD A,R & A$\leftarrow$R & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & IFF2 & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 2 & 9 & & \\ \multicolumn{10}{c}{} & 01 & 011 & 111 & 5F & \multicolumn{3}{c}{} & & \\ LD I,A & I$\leftarrow$A & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 101 & ED & 2 & 2 & 9 & & \\ \multicolumn{10}{c}{} & 01 & 000 & 111 & 47 & \multicolumn{3}{c}{} & & \\ LD R,A & R$\leftarrow$A & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 101 & ED & 2 & 2 & 9 & & \\ \multicolumn{10}{c}{} & 01 & 001 & 111 & 57 & \multicolumn{3}{c}{} & & \\ \hline \end{tabular} } \section{16-Bit Load Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline LD dd,nn & dd$\leftarrow$nn & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & dd0 & 001 & & 3 & 3 & 10 & dd & Reg\\ \cline{18-19} \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 00 & BC\\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 01 & DE\\ LD IX,nn & IX$\leftarrow$nn & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 4 & 4 & 14 & 10 & HL\\ \multicolumn{10}{c}{} & 00 & 100 & 001 & 21 & \multicolumn{3}{c}{} & 11 & SP\\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD IY,nn & IX$\leftarrow$nn & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 4 & 4 & 14 & & \\ \multicolumn{10}{c}{} & 00 & 100 & 001 & 21 & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD HL,(nn) & H$\leftarrow$(nn+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 101 & 010 & 2A & 3 & 5 & 16 & & \\ & L$\leftarrow$(nn) & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD dd,(nn) & ddh$\leftarrow$(nn+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 101 & ED & 4 & 6 & 20 & & \\ & ddl$\leftarrow$(nn) & \multicolumn{8}{c}{} & 01 & dd1 & 011 & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD IX,(nn) & IXh$\leftarrow$(nn+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 4 & 6 & 20 & & \\ & IXl$\leftarrow$(nn) & \multicolumn{8}{c}{} & 00 & 101 & 010 & 2A & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD IY,(nn) & IYh$\leftarrow$(nn+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 4 & 6 & 20 & & \\ & IYl$\leftarrow$(nn) & \multicolumn{8}{c}{} & 00 & 101 & 010 & 2A & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD (nn),HL & (nn+1)$\leftarrow$H & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 100 & 010 & 22 & 3 & 5 & 16 & & \\ & (nn)$\leftarrow$L & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD (nn),dd & (nn+1)$\leftarrow$ddh & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 101 & ED & 4 & 6 & 20 & & \\ & (nn)$\leftarrow$ddl & \multicolumn{8}{c}{} & 01 & dd0 & 011 & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD (nn),IX & (nn+1)$\leftarrow$IXh & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 4 & 6 & 20 & & \\ & (nn)$\leftarrow$IXl & \multicolumn{8}{c}{} & 00 & 100 & 010 & 22 & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD (nn),IY & (nn+1)$\leftarrow$IYh & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 4 & 6 & 20 & & \\ & (nn)$\leftarrow$IYl & \multicolumn{8}{c}{} & 00 & 100 & 010 & 22 & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & & \\ LD SP,HL & SP$\leftarrow$HL & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 001 & F9 & 1 & 1 & 6 & & \\ LD SP,IX & SP$\leftarrow$IX & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 2 & 2 & 10 & & \\ \multicolumn{10}{c}{} & 11 & 111 & 001 & F9 & \multicolumn{3}{c}{} & & \\ LD SP,IY & SP$\leftarrow$IY & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 2 & 2 & 10 & & \\ \multicolumn{10}{c}{} & 11 & 111 & 001 & F9 & \multicolumn{3}{c}{} & & \\ \hline \end{tabular} } (continued) \\ {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline PUSH qq & (SP-2)$\leftarrow$qql & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & qq0 & 101 & & 1 & 3 & 11 & qq & Reg\\ \cline{18-19} & (SP-1)$\leftarrow$qqh & \multicolumn{15}{c}{} & 00 & BC\\ & SP$\leftarrow$SP-2 & \multicolumn{15}{c}{} & 01 & DE\\ PUSH IX & (SP-2)$\leftarrow$IXl & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 2 & 4 & 15 & 10 & HL\\ & (SP-1)$\leftarrow$IXh & \multicolumn{8}{c}{} & 11 & 100 & 101 & E5 & \multicolumn{3}{c}{} & 11 & AF\\ & SP$\leftarrow$SP-2 & \multicolumn{15}{c}{} & & \\ PUSH IY & (SP-2)$\leftarrow$IYl & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 2 & 4 & 15 & & \\ & (SP-1)$\leftarrow$IYh & \multicolumn{8}{c}{} & 11 & 100 & 101 & E5 & \multicolumn{3}{c}{} & & \\ & SP$\leftarrow$SP-2 & \multicolumn{15}{c}{} & & \\ POP qq & qqh$\leftarrow$(SP+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & qq0 & 001 & & 1 & 3 & 10 & & \\ & qql$\leftarrow$(SP) & \multicolumn{15}{c}{} & & \\ & SP$\leftarrow$SP+2 & \multicolumn{15}{c}{} & & \\ POP IX & IXh$\leftarrow$(SP+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 2 & 4 & 14 & & \\ & IXl$\leftarrow$(SP) & \multicolumn{8}{c}{} & 11 & 100 & 001 & E1 & \multicolumn{3}{c}{} & & \\ & SP$\leftarrow$SP+2 & \multicolumn{15}{c}{} & & \\ POP IY & IYh$\leftarrow$(SP+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 2 & 4 & 14 & & \\ & IYl$\leftarrow$(SP) & \multicolumn{8}{c}{} & 11 & 100 & 001 & E1 & \multicolumn{3}{c}{} & & \\ & SP$\leftarrow$SP+2 & \multicolumn{15}{c}{} & & \\ \hline \end{tabular} } \section{Exchange, Block Transfer, Block Search Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline EX DE,HL & DE$\leftrightarrow$HL & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 011 & E8 & 1 & 1 & 4 & & \\ EX AF,AF' & AF$\leftrightarrow$AF' & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 001 & 000 & 08 & 1 & 1 & 4 & & \\ EXX & BC$\leftrightarrow$BC' & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 001 & D8 & 1 & 1 & 4 & & \\ & DE$\leftrightarrow$DE' & \multicolumn{15}{c}{} & & \\ & HL$\leftrightarrow$HL' & \multicolumn{15}{c}{} & & \\ EX (SP),HL & H$\leftrightarrow$(SP+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 100 & 011 & E3 & 1 & 5 & 19 & & \\ & L$\leftrightarrow$(SP) & \multicolumn{15}{c}{} & & \\ EX (SP),IX & IXh$\leftrightarrow$(SP+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 2 & 6 & 23 & & \\ & IXl$\leftrightarrow$(SP) & \multicolumn{8}{c}{} & 11 & 100 & 011 & \multicolumn{4}{c}{} & & \\ EX (SP),IY & IYh$\leftrightarrow$(SP+1) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 2 & 6 & 23 & & \\ & IYl$\leftrightarrow$(SP) & \multicolumn{8}{c}{} & 11 & 100 & 011 & \multicolumn{4}{c}{} & & \\ LDI & (DE)$\leftarrow$(HL) & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[4] & 0 & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[1] & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 4 & 16 & & \\ & DE$\leftarrow$DE+1 & \multicolumn{8}{c}{} & 10 & 100 & 000 & A0 & \multicolumn{3}{c}{} & & \\ & HL$\leftarrow$HL+1 & \multicolumn{15}{c}{} & & \\ & BC$\leftarrow$BC-1 & \multicolumn{15}{c}{} & & \\ LDIR & (DE)$\leftarrow$(HL) & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[4] & 0 & $\updownarrow$\footnotemark[4] & 0\footnotemark[2] & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 5 & 21 & \multicolumn{2}{l}{if BC$\not=$0} \\ & DE$\leftarrow$DE+1 & \multicolumn{8}{c}{} & 10 & 110 & 000 & B0 & 2 & 4 & 16 & \multicolumn{2}{l}{if BC=0} \\ & HL$\leftarrow$HL+1 & \multicolumn{15}{c}{} & & \\ & BC$\leftarrow$BC-1 & \multicolumn{15}{c}{} & & \\ & Repeat until& \multicolumn{15}{c}{} & & \\ & BC=0 & \multicolumn{15}{c}{} & & \\ LDD & (DE)$\leftarrow$(HL) & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[4] & 0 & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[1] & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 4 & 16 & & \\ & DE$\leftarrow$DE-1 & \multicolumn{8}{c}{} & 10 & 101 & 000 & A8 & \multicolumn{3}{c}{} & & \\ & HL$\leftarrow$HL-1 & \multicolumn{15}{c}{} & & \\ & BC$\leftarrow$BC-1 & \multicolumn{15}{c}{} & & \\ LDDR & (DE)$\leftarrow$(HL) & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[4] & 0 & $\updownarrow$\footnotemark[4] & 0\footnotemark[2] & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 5 & 21 & \multicolumn{2}{l}{if BC$\not=$0} \\ & DE$\leftarrow$DE-1 & \multicolumn{8}{c}{} & 10 & 111 & 000 & B8 & 2 & 4 & 16 & \multicolumn{2}{l}{if BC=0} \\ & HL$\leftarrow$HL-1 & \multicolumn{15}{c}{} & & \\ & BC$\leftarrow$BC-1 & \multicolumn{15}{c}{} & & \\ & Repeat until& \multicolumn{15}{c}{} & & \\ & BC=0 & \multicolumn{15}{c}{} & & \\ CPI & A-(HL) & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[3] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[1] & 1 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 4 & 16 & & \\ & HL$\leftarrow$HL+1 & \multicolumn{8}{c}{} & 10 & 100 & 001 & A1 & \multicolumn{3}{c}{} & & \\ & BC$\leftarrow$BC-1 & \multicolumn{15}{c}{} & & \\ CPIR & A-(HL) & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[3] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[1] & 1 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 5 & 21 & \multicolumn{2}{l}{if BC$\not=$0 and} \\ \multicolumn{17}{c}{} & \multicolumn{2}{l}{A$\not=$(HL)} \\ & HL$\leftarrow$HL+1 & \multicolumn{8}{c}{} & 10 & 110 & 001 & B1 & 2 & 4 & 18 & \multicolumn{2}{l}{if BC=0 or} \\ & BC$\leftarrow$BC-1 & \multicolumn{15}{c}{} & \multicolumn{2}{l}{A=(HL)} \\ & Repeat until& \multicolumn{15}{c}{} & & \\ & A=(HL) or & \multicolumn{15}{c}{} & & \\ & BC=0 & \multicolumn{15}{c}{} & & \\ CPD & A-(HL) & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[3] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[1] & 1 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 4 & 16 & & \\ & HL$\leftarrow$HL-1 & \multicolumn{8}{c}{} & 10 & 101 & 001 & A9 & \multicolumn{3}{c}{} & & \\ & BC$\leftarrow$BC-1 & \multicolumn{15}{c}{} & & \\ CPDR & A-(HL) & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[3] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[1] & 1 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 5 & 21 & \multicolumn{2}{l}{if BC$\not=$0 and} \\ \multicolumn{17}{c}{} & \multicolumn{2}{l}{A$\not=$(HL)} \\ & HL$\leftarrow$HL-1 & \multicolumn{8}{c}{} & 10 & 111 & 001 & B9 & 2 & 4 & 18 & \multicolumn{2}{l}{if BC=0 or} \\ & BC$\leftarrow$BC-1 & \multicolumn{15}{c}{} & \multicolumn{2}{l}{A=(HL)} \\ & Repeat until& \multicolumn{15}{c}{} & & \\ & A=(HL) or & \multicolumn{15}{c}{} & & \\ & BC=0 & \multicolumn{15}{c}{} & & \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[1]PF is 0 the result of BC-1=0, otherwise PF is set.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[2]PF is 0 only at completion of the instruction.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[3]ZF is set if A=(HL), otherwise ZF is reset.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[4]See section \ref{block_mem} for a description.}} \\ \hline \end{tabular} } \section{8-Bit Arithmetic and Logical Group} \setlength{\textwidth}{18cm} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline ADD A,r & A$\leftarrow$A+r & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\updownarrow$ & 10 & \fbox{000} & r & & 1 & 1 & 4 & r & Reg\\ \cline{18-19} ADD A,p & A$\leftarrow$A+p & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\updownarrow$ & 11 & 011 & 101 & DD & 2 & 2 & 8 & 000 & B \\ \multicolumn{10}{c}{} & 10 & \fbox{000} & p & \multicolumn{4}{c}{} & 001 & C \\ ADD A,q & A$\leftarrow$A+q & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\updownarrow$ & 11 & 111 & 101 & FD & 2 & 2 & 8 & 010 & D \\ \multicolumn{10}{c}{} & 10 & \fbox{000} & q & \multicolumn{4}{c}{} & 011 & E \\ ADD A,n & A$\leftarrow$A+n & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\updownarrow$ & 11 & \fbox{000} & 110 & & 2 & 2 & 7 & 100 & H \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 101 & L \\ ADD A,(HL) & A$\leftarrow$A+(HL) & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\updownarrow$ & 10 & \fbox{000} & 110 & & 1 & 2 & 7 & 111 & A \\ ADD A,(IX+d) & A$\leftarrow$A+(IX+d) & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\updownarrow$ & 11 & 011 & 101 & DD & 3 & 5 & 19 & & \\ \multicolumn{10}{c}{} & 10 & \fbox{000} & 110 & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & p & Reg \\ \cline{18-19} ADD A,(IY+d) & A$\leftarrow$A+(IY+d) & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\updownarrow$ & 11 & 111 & 101 & FD & 3 & 5 & 19 & 000 & B \\ \multicolumn{10}{c}{} & 10 & \fbox{000} & 110 & \multicolumn{4}{c}{} & 001 & C \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & 010 & D \\ ADC A,s & A$\leftarrow$A+s+CF & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\updownarrow$ & & \fbox{001} & \multicolumn{5}{c}{} & 011 & E \\ SUB s & A$\leftarrow$A-s & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 1 & $\updownarrow$ & & \fbox{010} & \multicolumn{5}{c}{} & 100 & IXh \\ SBC s & A$\leftarrow$A-s-CF & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 1 & $\updownarrow$ & & \fbox{011} & \multicolumn{5}{c}{} & 101 & IXl \\ AND s & A$\leftarrow$A$\wedge$s & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 1 & $\updownarrow$ & PF & 0 & 0 & & \fbox{100} & \multicolumn{5}{c}{} & 111 & A \\ OR s & A$\leftarrow$A$\vee$s & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & 0 & & \fbox{110} & \multicolumn{5}{c}{} & & \\ XOR s & A$\leftarrow$A$\bullet$s & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & 0 & & \fbox{101} & \multicolumn{5}{c}{} & & \\ CP s & A-s & $\updownarrow$ & $\updownarrow$ & $\updownarrow$\footnotemark[1] & $\updownarrow$ & $\updownarrow$\footnotemark[1] & VF & 1 & $\updownarrow$ & & \fbox{111} & \multicolumn{5}{c}{} & q & Reg \\ \cline{18-19} INC r & r$\leftarrow$r+1 & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\bullet$ & 00 & r & \fbox{100} & & 1 & 1 & 4 & 000 & B \\ INC p & p$\leftarrow$p+1 & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\bullet$ & 11 & 011 & 101 & DD & 2 & 2 & 8 & 001 & C \\ \multicolumn{10}{c}{} & 00 & p & \fbox{100} & \multicolumn{4}{c}{} & 010 & D \\ INC q & q$\leftarrow$q+1 & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\bullet$ & 11 & 111 & 101 & FD & 2 & 2 & 8 & 011 & E \\ \multicolumn{10}{c}{} & 00 & q & \fbox{100} & \multicolumn{4}{c}{} & 100 & IYh \\ INC (HL) & (HL)$\leftarrow$(HL)+1 & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\bullet$ & 00 & 110 & \fbox{100} & & 1 & 3 & 11 & 101 & IYl \\ INC (IX+d) & (IX+d)$\leftarrow$(IX+d)+1 & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\bullet$ & 11 & 011 & 101 & DD & 3 & 6 & 26 & 111 & A \\ \multicolumn{10}{c}{} & 00 & 110 & \fbox{100} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ INC (IY+d) & (IY+d)$\leftarrow$(IY+d)+1 & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 0 & $\bullet$ & 11 & 111 & 101 & FD & 3 & 6 & 26 & & \\ \multicolumn{10}{c}{} & 00 & 110 & \fbox{100} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ DEC m & m$\leftarrow$m-1 & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 1 & $\bullet$ & & & \fbox{101} & & & & & & \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[1]YF and XF flags are copied from the operand s, not the result A-s}} \\ & \multicolumn{18}{l}{\parbox{12cm}{s is any of r, p, q, n, (HL), (IX+d), (IY+d) as shown for ADD. The indicated bits replace the \fbox{000} in the ADD set above}} \\ & \multicolumn{18}{l}{\parbox{12cm}{m is any of r, p, q, (HL), (IX+d), (IY+d) as shown for INC. Replace \fbox{100} with \fbox{101} in opcode}} \\ \hline \end{tabular} } \section{General-Purpose Arithmetic and CPU Control Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline DAA & & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & PF & $\bullet$ & $\updownarrow$ & 00 & 100 & 111 & 27 & 1 & 1 & 4 & \multicolumn{2}{l}{Decimal adjust} \\ \multicolumn{17}{c}{} & \multicolumn{2}{l}{accumulator} \\ CPL & A$\leftarrow\mathtt{\overline{A}}$ & $\bullet$ & $\bullet$ & $\updownarrow$ & 1 & $\updownarrow$ & $\bullet$ & 1 & $\bullet$ & 00 & 101 & 111 & 2F & 1 & 1 & 4 & \multicolumn{2}{l}{Compliment} \\ NEG & A$\leftarrow$0-A & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & VF & 1 & $\updownarrow$ & 11 & 011 & 101 & ED & 2 & 2 & 8 & \multicolumn{2}{l}{Negate} \\ \multicolumn{10}{c}{} & 01 & 000 & 100 & 44 & \multicolumn{3}{c}{} & & \\ CCF & CF$\leftarrow\mathtt{\overline{CF}}$ & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[1] & $\bullet$ & 0 & $\updownarrow$ & 00 & 111 & 111 & 3F & 1 & 1 & 4 & & \\ SCF & CF$\leftarrow$1 & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[1] & 0 & $\updownarrow$\footnotemark[1] & $\bullet$ & 0 & 1 & 00 & 110 & 111 & 37 & 1 & 1 & 4 & & \\ NOP & & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 000 & 000 & 00 & 1 & 1 & 4 & & \\ HALT & & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 01 & 110 & 110 & 76 & 1 & 1 & 4 & & \\ DI\footnotemark[3] & IFF1,2$\leftarrow$0 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 110 & 011 & F3 & 1 & 1 & 4 & & \\ EI\footnotemark[3] & IFF1,2$\leftarrow$1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 011 & FB & 1 & 1 & 4 & & \\ IM 0\footnotemark[4] & & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & ED & 2 & 2 & 8 & & \\ \multicolumn{10}{c}{} & 01 & 000 & 110 & 46 & \multicolumn{3}{c}{} & & \\ IM 1\footnotemark[4] & & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & ED & 2 & 2 & 8 & & \\ \multicolumn{10}{c}{} & 01 & 010 & 110 & 56 & \multicolumn{3}{c}{} & & \\ IM 2\footnotemark[4] & & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & ED & 2 & 2 & 8 & & \\ \multicolumn{10}{c}{} & 01 & 011 & 110 & 5E & \multicolumn{3}{c}{} & & \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[1]YF and XF are copied from register A.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[2]HF is like CF before the instruction.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[3]No interrupts are accepted directly after EI or DI.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[4]This instruction has other undocumented opcodes.}} \\ \hline \end{tabular} } \section{16-Bit Arithmetic Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline ADD HL,ss & HL$\leftarrow$HL+ss & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & $\bullet$ & 0 & $\updownarrow$\footnotemark[1] & 01 & ss1 & 001 & & 1 & 3 & 11 & ss & Reg \\ \cline{18-19} ADC HL,ss & HL$\leftarrow$HL+ss+CF & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & VF\footnotemark[1] & 0 & $\updownarrow$\footnotemark[1] & 11 & 011 & 101 & ED & 2 & 4 & 15 & 00 & BC \\ \multicolumn{10}{c}{} & 01 & ss1 & 010 & & \multicolumn{3}{c}{} & 01 & DE \\ SBC HL,ss & HL$\leftarrow$HL-ss-CF & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & VF\footnotemark[1] & 0 & $\updownarrow$\footnotemark[1] & 11 & 011 & 101 & ED & 2 & 4 & 15 & 10 & HL \\ \multicolumn{10}{c}{} & 01 & ss0 & 010 & & \multicolumn{3}{c}{} & 11 & SP \\ ADD IX,pp & IX$\leftarrow$IX+pp & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & $\bullet$ & 0 & $\updownarrow$\footnotemark[1] & 11 & 011 & 110 & DD & 2 & 4 & 15 & & \\ \multicolumn{10}{c}{} & 01 & pp1 & 001 & & \multicolumn{3}{c}{} & pp & Reg \\ \cline{18-19} ADD IY,qq & IY$\leftarrow$IY+qq & $\bullet$ & $\bullet$ & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[2] & $\bullet$ & 0 & $\updownarrow$\footnotemark[1] & 11 & 111 & 110 & FD & 2 & 4 & 15 & 00 & BC \\ \multicolumn{10}{c}{} & 01 & pp1 & 001 & & \multicolumn{3}{c}{} & 01 & DE \\ INC ss & ss$\leftarrow$ss+1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & ss0 & 011 & & 1 & 1 & 6 & 10 & IX \\ INC IX & IX$\leftarrow$IX+1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 2 & 2 & 10 & 11 & SP \\ \multicolumn{10}{c}{} & 00 & 100 & 011 & 23 & \multicolumn{3}{c}{} & & \\ INC IY & IY$\leftarrow$IY+1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 2 & 2 & 10 & qq & Reg \\ \cline{18-19} \multicolumn{10}{c}{} & 00 & 100 & 011 & 23 & \multicolumn{3}{c}{} & 00 & BC \\ DEC ss & ss$\leftarrow$ss-1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & ss1 & 011 & & 1 & 1 & 6 & 01 & DE \\ DEC IX & IX$\leftarrow$IX-1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 2 & 2 & 10 & 10 & HL \\ \multicolumn{10}{c}{} & 00 & 101 & 011 & 2B & \multicolumn{3}{c}{} & 11 & SP \\ DEC IY & IY$\leftarrow$IY-1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 2 & 2 & 10 & & \\ \multicolumn{10}{c}{} & 00 & 101 & 011 & 2B & \multicolumn{3}{c}{} & & \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[1]Flag is affected by the 16 bit result.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[2]Flag is affected by the high-byte addition.}} \\ \hline \end{tabular} } \section{Rotate and Shift Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline RLCA & \setlength{\unitlength}{0.9mm} \begin{picture}(17,5) \put(0,0){\framebox(4,3){CF}} \put(8,0){\framebox(7,3){7$\leftarrow$0}} \put(8,1.5){\vector(-1,0){4}} \put(6,1.5){\line(0,1){2.5}} \put(6,4){\line(1,0){11}} \put(17,4){\line(0,-1){2.5}} \put(17,1.5){\vector(-1,0){2}} \end{picture} & $\bullet$ & $\bullet$ & $\updownarrow$ & 0 & $\updownarrow$ & $\bullet$ & 0 & $\updownarrow$ & 00 & 000 & 111 & 07 & 1 & 1 & 4 & & \\ RLA & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(2,0){\framebox(4,3){CF}} \put(9,0){\framebox(7,3){7$\leftarrow$0}} \put(9,1.5){\vector(-1,0){3}} \put(2,1.5){\line(-1,0){2}} \put(0,1.5){\line(0,1){2.5}} \put(0,4){\line(1,0){17.5}} \put(17.5,4){\line(0,-1){2.5}} \put(17.5,1.5){\vector(-1,0){1.5}} \end{picture} & $\bullet$ & $\bullet$ & $\updownarrow$ & 0 & $\updownarrow$ & $\bullet$ & 0 & $\updownarrow$ & 00 & 010 & 111 & 17 & 1 & 1 & 4 & & \\ RRCA & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(13,0){\framebox(4,3){CF}} \put(2,0){\framebox(7,3){7$\leftarrow$0}} \put(0,1.5){\vector(1,0){2}} \put(9,1.5){\vector(1,0){4}} \put(0,1.5){\line(0,1){2.5}} \put(0,4){\line(1,0){11}} \put(11,4){\line(0,-1){2.5}} \end{picture} & $\bullet$ & $\bullet$ & $\updownarrow$ & 0 & $\updownarrow$ & $\bullet$ & 0 & $\updownarrow$ & 00 & 001 & 111 & 0F & 1 & 1 & 4 & & \\ RRA & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(12,0){\framebox(4,3){CF}} \put(2,0){\framebox(7,3){7$\leftarrow$0}} \put(0,1.5){\vector(1,0){2}} \put(9,1.5){\vector(1,0){3}} \put(0,1.5){\line(0,1){2.5}} \put(0,4){\line(1,0){17.5}} \put(17.5,4){\line(0,-1){2.5}} \put(16,1.5){\line(1,0){1.5}} \end{picture} & $\bullet$ & $\bullet$ & $\updownarrow$ & 0 & $\updownarrow$ & $\bullet$ & 0 & $\updownarrow$ & 00 & 011 & 111 & 1F & 1 & 1 & 4 & & \\ RLC r & \setlength{\unitlength}{0.9mm} \begin{picture}(17,5) \put(0,0){\framebox(4,3){CF}} \put(8,0){\framebox(7,3){7$\leftarrow$0}} \put(8,1.5){\vector(-1,0){4}} \put(6,1.5){\line(0,1){2.5}} \put(6,4){\line(1,0){11}} \put(17,4){\line(0,-1){2.5}} \put(17,1.5){\vector(-1,0){2}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & 11 & 001 & 011 & CB & 2 & 2 & 8 & r & Reg \\ \cline{18-19} \multicolumn{10}{c}{} & 00 & \fbox{000} & r & \multicolumn{4}{c}{} & 000 & B \\ RLC (HL) & \setlength{\unitlength}{0.9mm} \begin{picture}(17,5) \put(0,0){\framebox(4,3){CF}} \put(8,0){\framebox(7,3){7$\leftarrow$0}} \put(8,1.5){\vector(-1,0){4}} \put(6,1.5){\line(0,1){2.5}} \put(6,4){\line(1,0){11}} \put(17,4){\line(0,-1){2.5}} \put(17,1.5){\vector(-1,0){2}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & 11 & 001 & 011 & CB & 2 & 4 & 15 & 001 & C \\ \multicolumn{10}{c}{} & 00 & \fbox{000} & 110 & \multicolumn{4}{c}{} & 010 & D \\ RLC (IX+d) & \setlength{\unitlength}{0.9mm} \begin{picture}(17,5) \put(0,0){\framebox(4,3){CF}} \put(8,0){\framebox(7,3){7$\leftarrow$0}} \put(8,1.5){\vector(-1,0){4}} \put(6,1.5){\line(0,1){2.5}} \put(6,4){\line(1,0){11}} \put(17,4){\line(0,-1){2.5}} \put(17,1.5){\vector(-1,0){2}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & 11 & 011 & 101 & DD & 4 & 6 & 23 & 011 & E \\ \multicolumn{10}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & 100 & H \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & 101 & L \\ \multicolumn{10}{c}{} & 00 & \fbox{000} & 110 & & \multicolumn{3}{c}{} & 111 & A \\ RLC (IY+d) & \setlength{\unitlength}{0.9mm} \begin{picture}(17,5) \put(0,0){\framebox(4,3){CF}} \put(8,0){\framebox(7,3){7$\leftarrow$0}} \put(8,1.5){\vector(-1,0){4}} \put(6,1.5){\line(0,1){2.5}} \put(6,4){\line(1,0){11}} \put(17,4){\line(0,-1){2.5}} \put(17,1.5){\vector(-1,0){2}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & 11 & 111 & 101 & FD & 4 & 6 & 23 & & \\ \multicolumn{10}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ & & \multicolumn{8}{c}{} & 00 & \fbox{000} & 110 & & \multicolumn{3}{c}{} & & \\ RLC (IX+d),r & r$\leftarrow$(IX+d) & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & 11 & 011 & 101 & DD & 4 & 6 & 23 & & \\ & RLC r & \multicolumn{8}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & & \\ & (IX+d)$\leftarrow$r & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ & & \multicolumn{8}{c}{} & 00 & \fbox{000} & r & & \multicolumn{3}{c}{} & & \\ RLC (IY+d),r & r$\leftarrow$(IY+d) & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & 11 & 111 & 101 & FD & 4 & 6 & 23 & & \\ & RLC r & \multicolumn{8}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & & \\ & (IY+d)$\leftarrow$r & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ & & \multicolumn{8}{c}{} & 00 & \fbox{000} & r & & \multicolumn{3}{c}{} & & \\ RL m & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(2,0){\framebox(4,3){CF}} \put(9,0){\framebox(7,3){7$\leftarrow$0}} \put(9,1.5){\vector(-1,0){3}} \put(2,1.5){\line(-1,0){2}} \put(0,1.5){\line(0,1){2.5}} \put(0,4){\line(1,0){17.5}} \put(17.5,4){\line(0,-1){2.5}} \put(17.5,1.5){\vector(-1,0){1.5}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & &\fbox{010} & \\ RRC m & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(13,0){\framebox(4,3){CF}} \put(2,0){\framebox(7,3){7$\leftarrow$0}} \put(0,1.5){\vector(1,0){2}} \put(9,1.5){\vector(1,0){4}} \put(0,1.5){\line(0,1){2.5}} \put(0,4){\line(1,0){11}} \put(11,4){\line(0,-1){2.5}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & &\fbox{001} & \\ RR m & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(12,0){\framebox(4,3){CF}} \put(2,0){\framebox(7,3){7$\leftarrow$0}} \put(0,1.5){\vector(1,0){2}} \put(9,1.5){\vector(1,0){3}} \put(0,1.5){\line(0,1){2.5}} \put(0,4){\line(1,0){17.5}} \put(17.5,4){\line(0,-1){2.5}} \put(16,1.5){\line(1,0){1.5}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & &\fbox{011} & \\ SLA m & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(0,0){\framebox(4,3){CF}} \put(7,0){\framebox(7,3){7$\leftarrow$0}} \put(7,1.5){\vector(-1,0){3}} \put(17,1.5){\vector(-1,0){3}} \put(16,0){\makebox(4,3){0}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & &\fbox{100} & \\ SLL m & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(0,0){\framebox(4,3){CF}} \put(7,0){\framebox(7,3){7$\leftarrow$0}} \put(7,1.5){\vector(-1,0){3}} \put(17,1.5){\vector(-1,0){3}} \put(16,0){\makebox(4,3){1}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & &\fbox{110} & \\ SRA m & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(13,0){\framebox(4,3){CF}} \put(3,0){\framebox(7,3){7$\rightarrow$0}} \put(10,1.5){\vector(1,0){3}} \put(1,1.5){\vector(1,0){2}} \put(1,-1.5){\line(0,1){3}} \put(1,-1.5){\line(1,0){2.5}} \put(3.5,-1.5){\line(0,1){1.5}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & &\fbox{101} & \\ SLA m & \setlength{\unitlength}{0.9mm} \begin{picture}(17,4) \put(-0.5,0){\makebox(1,3){0}} \put(13,0){\framebox(4,3){CF}} \put(3,0){\framebox(7,3){7$\rightarrow$0}} \put(10,1.5){\vector(1,0){3}} \put(1,1.5){\vector(1,0){2}} \end{picture} & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\updownarrow$ & &\fbox{111} & \\ RLD & & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 5 & 18 & & \\ \multicolumn{10}{c}{} & 01 & 101 & 111 & 6F & \multicolumn{3}{c}{} & & \\ RRD & & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 5 & 18 & & \\ \multicolumn{10}{c}{} & 01 & 100 & 111 & 67 & \multicolumn{3}{c}{} & & \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{m is one of r,(HL),(IX+d),(IY+d). To form new opcode replace \fbox{000} of RLCs with shown code.}} \\ \hline \end{tabular} } \section{Bit Set, Reset and Test Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline BIT b,r & ZF$\leftarrow\mathtt{\overline{r_b}}$ & $\updownarrow$\footnotemark[1] & $\updownarrow$ & $\updownarrow$\footnotemark[1] & 1 & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & 0 & $\bullet$ & 11 & 001 & 011 & CB & 2 & 2 & 8 & r & Reg \\ \cline{18-19} \multicolumn{10}{c}{} & 01 & b & r & & \multicolumn{3}{c}{} & 000 & B \\ BIT b,(HL) & \mbox{ZF$\leftarrow\mathtt{\overline{(HL)_b}}$} & $\updownarrow$\footnotemark[1] & $\updownarrow$ & $\updownarrow$\footnotemark[1] & 1 & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & 0 & $\bullet$ & 11 & 001 & 011 & CB & 2 & 3 & 12 & 001 & C \\ \multicolumn{10}{c}{} & 01 & b & 110 & & \multicolumn{3}{c}{} & 010 & D \\ BIT b,(IX+d)\footnotemark[2] & ZF$\leftarrow\mathtt{\overline{(IX+d)_b}}$ & $\updownarrow$\footnotemark[1] & $\updownarrow$ & $\updownarrow$\footnotemark[1] & 1 & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & 0 & $\bullet$ & 11 & 011 & 101 & DD & 4 & 8 & 20 & 011 & E \\ \multicolumn{10}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & 100 & H \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & 101 & L \\ \multicolumn{10}{c}{} & 01 & b & 110 & & \multicolumn{3}{c}{} & 111 & A \\ BIT b,(IY+d)\footnotemark[2] & ZF$\leftarrow\mathtt{\overline{(IY+d)_b}}$ & $\updownarrow$\footnotemark[1] & $\updownarrow$ & $\updownarrow$\footnotemark[1] & 1 & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & 0 & $\bullet$ & 11 & 111 & 101 & FD & 4 & 8 & 20 & & \\ \multicolumn{10}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & 01 & b & 110 & & \multicolumn{3}{c}{} & & \\ SET b,r & $\mathtt{r_b}\leftarrow$1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 001 & 011 & CB & 2 & 2 & 8 & b & Bit \\ \cline{18-19} \multicolumn{10}{c}{} & \fbox{11} & b & r & & \multicolumn{3}{c}{} & 000 & 0 \\ SET b,(HL) & $\mathtt{(HL)_b}\leftarrow$1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 001 & 011 & CB & 2 & 4 & 15 & 001 & 1\\ \multicolumn{10}{c}{} & \fbox{11} & b & 110 & & \multicolumn{3}{c}{} & 010 & 2 \\ SET b,(IX+d) & $\mathtt{(IX+d)_b}\leftarrow$1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 4 & 8 & 23 & 011 & 3 \\ \multicolumn{10}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & 100 & 4 \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & 101 & 5 \\ \multicolumn{10}{c}{} & \fbox{11} & b & 110 & & \multicolumn{3}{c}{} & 110 & 6 \\ SET b,(IY+d) & $\mathtt{(IY+d)_b}\leftarrow$1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 4 & 8 & 23 & 111 & 7 \\ \multicolumn{10}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & & \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \fbox{11} & b & 110 & & \multicolumn{3}{c}{} & & \\ SET b,(IX+d),r & r$\leftarrow$(IX+d) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 4 & 8 & 23 & & \\ & $\mathtt{r_b}\leftarrow$1 & \multicolumn{8}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & & \\ & (IX+d)$\leftarrow$r & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \fbox{11} & b & r & & \multicolumn{3}{c}{} & & \\ SET b,(IY+d),r & r$\leftarrow$(IY+d) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 4 & 8 & 23 & & \\ & $\mathtt{r_b}\leftarrow$1 & \multicolumn{8}{c}{} & 11 & 001 & 011 & CB & \multicolumn{3}{c}{} & & \\ & (IY+d)$\leftarrow$r & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ d $\rightarrow$} & \multicolumn{4}{c}{} & & \\ \multicolumn{10}{c}{} & \fbox{11} & b & r & & \multicolumn{3}{c}{} & & \\ RES b,m & $\mathtt{m_b}\leftarrow$0 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & \fbox{10} & & \multicolumn{4}{c}{} & & \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[1]See section \ref{bit_flags} for a complete description.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[2]Instruction has other undocumented opcodes.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{m is one of r, (HL), (IX+d), (IY+d). To form RES instruction, replace \fbox{11} with \fbox{10}.}} \\ \hline \end{tabular} } \section{Jump Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline JP nn & PC$\leftarrow$nn & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 000 & 011 & C3 & 3 & 3 & 10 & cc & Condition \\ \cline{18-19} \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 000 & NZ \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 001 & Z \\ JP cc,nn & if cc & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & cc & 010 & & 3 & 3 & 10 & 010 & NC \\ & PC$\leftarrow$nn & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 011 & C \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & \multicolumn{4}{c}{} & 100 & PO \\ JR e & PC$\leftarrow$PC+e & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 011 & 000 & 18 & 2 & 3 & 12 & 101 & PE \\ \multicolumn{10}{c}{} & \multicolumn{3}{c}{$\leftarrow$ e-2 $\rightarrow$} & \multicolumn{4}{c}{} & 110 & P \\ \multicolumn{17}{c}{} & 111 & M \\ \multicolumn{17}{c}{} & & \\ JR ss,e & if ss & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 1ss & 000 & & 2 & 3 & 12 & \multicolumn{2}{l}{if ss is true} \\ & PC$\leftarrow$PC+e & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ e-2 $\rightarrow$} & & 2 & 2 & 7 & \multicolumn{2}{l}{if ss is false} \\ JP (HL) & PC$\leftarrow$HL & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 001 & E9 & 1 & 1 & 4 & & \\ JP (IX) & PC$\leftarrow$IX & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 101 & DD & 2 & 2 & 8 & ss & Condition \\ \cline{18-19} \multicolumn{10}{c}{} & 11 & 101 & 001 & E9 & \multicolumn{3}{c}{} & 11 & C \\ JP (IY) & PC$\leftarrow$IY & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 111 & 101 & FD & 2 & 2 & 8 & 10 & NC \\ \multicolumn{10}{c}{} & 11 & 101 & 001 & E9 & \multicolumn{3}{c}{} & 01 & Z \\ \multicolumn{17}{c}{} & 00 & NZ \\ \multicolumn{17}{c}{} & & \\ DJNZ e & B$\leftarrow$B-1 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 00 & 010 & 000 & 10 & 2 & 2 & 10 & \multicolumn{2}{l}{if B=0} \\ & if B$\not=$0 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ e-2 $\rightarrow$} & & & & & & \\ & PC$\leftarrow$PC+e & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & 2 & 3 & 13 & \multicolumn{2}{l}{if B$\not=$0} \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{e is a signed two-compliment in the range -127, 129.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{e-2 in the opcode provides an effective number of PC+e as PC is incremented by two prior to the addition of e.}} \\[1ex] \hline \end{tabular} } \section{Call and Return Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline CALL nn & (SP-1)$\leftarrow$PCh & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 001 & 101 & CD & 3 & 5 & 17 & & \\ & (SP-2)$\leftarrow$PCl & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & & & & & & \\ & SP$\leftarrow$SP-2 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & & & & & & \\ & PC$\leftarrow$nn & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & & \\ CALL cc,nn & if cc is true & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & cc & 100 & & 3 & 3 & 10 & \multicolumn{2}{l}{if cc is false} \\ & (SP-1)$\leftarrow$PCh & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & & 3 & 5 & 17 & \multicolumn{2}{l}{if cc is true} \\ & (SP-2)$\leftarrow$PCl & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & & & & & & \\ & SP$\leftarrow$SP-2 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & & \\ & PC$\leftarrow$nn & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & & \\ RET & PCl$\leftarrow$(SP) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 001 & 001 & C9 & 1 & 3 & 10 & & \\ & PCh$\leftarrow$(SP+1) & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & & \\ & SP$\leftarrow$SP+2 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & & \\ RET cc & if cc is true & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & cc & 000 & & 1 & 1 & 5 & \multicolumn{2}{l}{if cc is false} \\ & PCl$\leftarrow$(SP) & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & 1 & 5 & 17 & \multicolumn{2}{l}{if cc is true} \\ & PCh$\leftarrow$(SP+1) & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & & \\ & SP$\leftarrow$SP+2 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & & \\ RETI\footnotemark[1] & PCl$\leftarrow$(SP) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 101 & ED & 2 & 4 & 14 & cc & Condition \\ \cline{18-19} & PCh$\leftarrow$(SP+1) & \multicolumn{8}{c}{} & 01 & 001 & 101 & 4D & & & & 000 & NZ \\ & SP$\leftarrow$SP+2 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 001 & Z \\ RETN\footnotemark[2] & PCl$\leftarrow$(SP) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 101 & ED & 2 & 4 & 14 & 010 & NC \\ & PCh$\leftarrow$(SP+1) & \multicolumn{8}{c}{} & 01 & 000 & 101 & 45 & & & & 011 & C \\ & SP$\leftarrow$SP+2 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 100 & PO \\ & IFF1$\leftarrow$IFF2 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 101 & PE \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 110 & P \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 111 & M \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & & \\ RST p & (SP-1)$\leftarrow$PCh & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & t & 111 & & 1 & 3 & 11 & t & p \\ \cline{18-19} & (SP-2)$\leftarrow$PCl & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & & & & & 000 & 0h\\ & SP$\leftarrow$SP-2 & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & & & & & 001 & 8h \\ & PC$\leftarrow$p & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 010 & 10h \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 011 & 18h \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 100 & 20h \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 101 & 28h \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 110 & 30h \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{} & & & & & 111 & 38h \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[1] RETI also copies IFF2 into IFF1, like RETN.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[2] This instruction has other undocumented opcodes.}} \\ \hline \end{tabular} } \section{Input and Output Group} {\tt \scriptsize \setlength{\fboxsep}{0.25mm} \setlength{\tabcolsep}{1mm} \begin{tabular}{llc@{ }c@{ }c@{ }c@{ }c@{ }c@{ }c@{ }cc@{ }c@{ }cccccll}\hline & \multicolumn{1}{c}{Symbolic} & \multicolumn{8}{c}{Flags} & \multicolumn{3}{c}{Opcode} & & & M & T & \\ Mnemonic & \multicolumn{1}{c}{Operation} & SF & ZF & YF & HF & XF & PF & NF & CF & 76 & 543 & 210 & Hex & Bytes & Cycles & States & \multicolumn{2}{l}{Comments} \\ \hline IN A,(n) & A$\leftarrow$(n) & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 011 & 011 & DB & 2 & 3 & 11 & r & Reg \\ \cline{18-19} & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & & & & & 000 & B \\ IN r,(C) & r$\leftarrow$(C) & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 3 & 12 & 001 & C \\ & & \multicolumn{8}{c}{} & 01 & r & 000 & & & & & 010 & D \\ IN F,(n) & $\leftarrow$(C) & $\updownarrow$ & $\updownarrow$ & $\updownarrow$ & 0 & $\updownarrow$ & PF & 0 & $\bullet$ & 11 & 101 & 101 & ED & 2 & 3 & 12 & 011 & E \\ & & \multicolumn{8}{c}{} & 01 & 110 & 000 & 70 & & & & 100 & H \\ INI & (HL)$\leftarrow$(C) & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[3] & $\updownarrow$\footnotemark[1] & X & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[3] & 11 & 101 & 101 & ED & 2 & 4 & 16 & 101 & L \\ & HL$\leftarrow$HL+1 & \multicolumn{8}{c}{} & 10 & 100 & 010 & A2 & & & & 111 & A \\ & B$\leftarrow$B-1 \\ INIR & (HL)$\leftarrow$(C) & 0 & 1 & 0 & $\updownarrow$\footnotemark[3] & 0 & X & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[3] & 11 & 101 & 101 & ED & 2 & 5 & 21 & \multicolumn{2}{l}{if B$\not=$0} \\ & HL$\leftarrow$HL+1 & \multicolumn{8}{c}{} & 10 & 110 & 010 & B2 & 2 & 4 & 16 & \multicolumn{2}{l}{if B=0} \\ & B$\leftarrow$B-1 \\ & Repeat until \\ & B=0 \\ IND & (HL)$\leftarrow$(C) & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[4] & $\updownarrow$\footnotemark[1] & X & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[4] & 11 & 101 & 101 & ED & 2 & 4 & 16 & & \\ & HL$\leftarrow$HL-1 & \multicolumn{8}{c}{} & 10 & 101 & 010 & AA & & & & & \\ & B$\leftarrow$B-1 \\ INDR & (HL)$\leftarrow$(C) & 0 & 1 & 0 & $\updownarrow$\footnotemark[4] & 0 & X & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[4] & 11 & 101 & 101 & ED & 2 & 5 & 21 & \multicolumn{2}{l}{if B$\not=$0} \\ & HL$\leftarrow$HL-1 & \multicolumn{8}{c}{} & 10 & 111 & 010 & BA & 2 & 4 & 16 & \multicolumn{2}{l}{if B=0} \\ & B$\leftarrow$B-1 \\ & Repeat until \\ & B=0 \\ OUT (n),A & (n)$\leftarrow$A & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 010 & 011 & D3 & 2 & 3 & 11 & & \\ & & \multicolumn{8}{c}{} & \multicolumn{3}{c}{$\leftarrow$ n $\rightarrow$} & & & & & & \\ OUT (C),r & (C)$\leftarrow$r & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 101 & ED & 2 & 3 & 12 & & \\ & & \multicolumn{8}{c}{} & 01 & r & 001 & & & & & & \\ OUT (C),0 & (C)$\leftarrow$0 & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & $\bullet$ & 11 & 101 & 101 & ED & 2 & 3 & 12 & & \\ & & \multicolumn{8}{c}{} & 01 & 110 & 001 & 71 & & & & & \\ OUTI & (C)$\leftarrow$(HL) & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[5] & $\updownarrow$\footnotemark[1] & X & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[5] & 11 & 101 & 101 & ED & 2 & 4 & 16 & & \\ & HL$\leftarrow$HL+1 & \multicolumn{8}{c}{} & 10 & 100 & 011 & A2 & & & & & \\ & B$\leftarrow$B-1 \\ OTIR & (C)$\leftarrow$(HL) & 0 & 1 & 0 & $\updownarrow$\footnotemark[5] & 0 & X & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[5] & 11 & 101 & 101 & ED & 2 & 5 & 21 & \multicolumn{2}{l}{if B$\not=$0} \\ & HL$\leftarrow$HL+1 & \multicolumn{8}{c}{} & 10 & 110 & 011 & B3 & 2 & 4 & 16 & \multicolumn{2}{l}{if B=0} \\ & B$\leftarrow$B-1 \\ & Repeat until \\ & B=0 \\ OUTD & (C)$\leftarrow$(HL) & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[1] & $\updownarrow$\footnotemark[5] & $\updownarrow$\footnotemark[1] & X & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[5] & 11 & 101 & 101 & ED & 2 & 4 & 16 & & \\ & HL$\leftarrow$HL-1 & \multicolumn{8}{c}{} & 10 & 101 & 011 & AA & & & & & \\ & B$\leftarrow$B-1 \\ OTDR & (C)$\leftarrow$(HL) & 0 & 1 & 0 & $\updownarrow$\footnotemark[5] & 0 & X & $\updownarrow$\footnotemark[2] & $\updownarrow$\footnotemark[5] & 11 & 101 & 101 & ED & 2 & 5 & 21 & \multicolumn{2}{l}{if B$\not=$0} \\ & HL$\leftarrow$HL-1 & \multicolumn{8}{c}{} & 10 & 111 & 011 & BB & 2 & 4 & 16 & \multicolumn{2}{l}{if B=0} \\ & B$\leftarrow$B-1 \\ & Repeat until \\ & B=0 \\ \hline Note: & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[1] flag is affected by the result of B$\leftarrow$B-1 as in DEC B.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[2] NF is a copy of bit 7 of the transferred byte.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[3] This flag contains the carry of (((C+1) AND 255)+(C)), see section \ref{block_io}.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[4] This flag contains the carry of (((C-1) AND 255)+(C)), see section \ref{block_io}.}} \\ & \multicolumn{18}{l}{\parbox{12cm}{\footnotemark[5] This flag contains the carry of (L+(C)), see section \ref{block_io}.}} \\ \hline \end{tabular} } \chapter{Instructions Sorted by Opcode} Any instruction marked with * is undocumented. \begin{multicols}{3} \scriptsize {\tt \begin{tabbing} 00{\qquad}{\qquad}{\quad}\=NOP\\ 01 n n\>LD BC,nn\\ 02\>LD (BC),A\\ 03\>INC BC\\ 04\>INC B\\ 05\>DEC B\\ 06 n\>LD B,n\\ 07\>RLCA\\ 08\>EX AF,AF'\\ 09\>ADD HL,BC\\ 0A\>LD A,(BC)\\ 0B\>DEC BC\\ 0C\>INC C\\ 0D\>DEC C\\ 0E n\>LD C,n\\ 0F\>RRCA\\ 10 e\>DJNZ (PC+e)\\ 11 n n\>LD DE,nn\\ 12\>LD (DE),A\\ 13\>INC DE\\ 14\>INC D\\ 15\>DEC D\\ 16 n\>LD D,n\\ 17\>RLA\\ 18 e\>JR (PC+e)\\ 19\>ADD HL,DE\\ 1A\>LD A,(DE)\\ 1B\>DEC DE\\ 1C\>INC E\\ 1D\>DEC E\\ 1E n\>LD E,n\\ 1F\>RRA\\ 20 e\>JR NZ,(PC+e)\\ 21 n n\>LD HL,nn\\ 22 n n\>LD (nn),HL\\ 23\>INC HL\\ 24\>INC H\\ 25\>DEC H\\ 26 n\>LD H,n\\ 27\>DAA\\ 28 e\>JR Z,(PC+e)\\ 29\>ADD HL,HL\\ 2A n n\>LD HL,(nn)\\ 2B\>DEC HL\\ 2C\>INC L\\ 2D\>DEC L\\ 2E n\>LD L,n\\ 2F\>CPL\\ 30 e\>JR NC,(PC+e)\\ 31 n n\>LD SP,nn\\ 32 n n\>LD (nn),A\\ 33\>INC SP\\ 34\>INC (HL)\\ 35\>DEC (HL)\\ 36 n\>LD (HL),n\\ 37\>SCF\\ 38 e\>JR C,(PC+e)\\ 39\>ADD HL,SP\\ 3A n n\>LD A,(nn)\\ 3B\>DEC SP\\ 3C\>INC A\\ 3D\>DEC A\\ 3E n\>LD A,n\\ 3F\>CCF\\ 40\>LD B,B\\ 41\>LD B,C\\ 42\>LD B,D\\ 43\>LD B,E\\ 44\>LD B,H\\ 45\>LD B,L\\ 46\>LD B,(HL)\\ 47\>LD B,A\\ 48\>LD C,B\\ 49\>LD C,C\\ 4A\>LD C,D\\ 4B\>LD C,E\\ 4C\>LD C,H\\ 4D\>LD C,L\\ 4E\>LD C,(HL)\\ 4F\>LD C,A\\ 50\>LD D,B\\ 51\>LD D,C\\ 52\>LD D,D\\ 53\>LD D,E\\ 54\>LD D,H\\ 55\>LD D,L\\ 56\>LD D,(HL)\\ 57\>LD D,A\\ 58\>LD E,B\\ 59\>LD E,C\\ 5A\>LD E,D\\ 5B\>LD E,E\\ 5C\>LD E,H\\ 5D\>LD E,L\\ 5E\>LD E,(HL)\\ 5F\>LD E,A\\ 60\>LD H,B\\ 61\>LD H,C\\ 62\>LD H,D\\ 63\>LD H,E\\ 64\>LD H,H\\ 65\>LD H,L\\ 66\>LD H,(HL)\\ 67\>LD H,A\\ 68\>LD L,B\\ 69\>LD L,C\\ 6A\>LD L,D\\ 6B\>LD L,E\\ 6C\>LD L,H\\ 6D\>LD L,L\\ 6E\>LD L,(HL)\\ 6F\>LD L,A\\ 70\>LD (HL),B\\ 71\>LD (HL),C\\ 72\>LD (HL),D\\ 73\>LD (HL),E\\ 74\>LD (HL),H\\ 75\>LD (HL),L\\ 76\>HALT\\ 77\>LD (HL),A\\ 78\>LD A,B\\ 79\>LD A,C\\ 7A\>LD A,D\\ 7B\>LD A,E\\ 7C\>LD A,H\\ 7D\>LD A,L\\ 7E\>LD A,(HL)\\ 7F\>LD A,A\\ 80\>ADD A,B\\ 81\>ADD A,C\\ 82\>ADD A,D\\ 83\>ADD A,E\\ 84\>ADD A,H\\ 85\>ADD A,L\\ 86\>ADD A,(HL)\\ 87\>ADD A,A\\ 88\>ADC A,B\\ 89\>ADC A,C\\ 8A\>ADC A,D\\ 8B\>ADC A,E\\ 8C\>ADC A,H\\ 8D\>ADC A,L\\ 8E\>ADC A,(HL)\\ 8F\>ADC A,A\\ 90\>SUB B\\ 91\>SUB C\\ 92\>SUB D\\ 93\>SUB E\\ 94\>SUB H\\ 95\>SUB L\\ 96\>SUB (HL)\\ 97\>SUB A\\ 98\>SBC A,B\\ 99\>SBC A,C\\ 9A\>SBC A,D\\ 9B\>SBC A,E\\ 9C\>SBC A,H\\ 9D\>SBC A,L\\ 9E\>SBC A,(HL)\\ 9F\>SBC A,A\\ A0\>AND B\\ A1\>AND C\\ A2\>AND D\\ A3\>AND E\\ A4\>AND H\\ A5\>AND L\\ A6\>AND (HL)\\ A7\>AND A\\ A8\>XOR B\\ A9\>XOR C\\ AA\>XOR D\\ AB\>XOR E\\ AC\>XOR H\\ AD\>XOR L\\ AE\>XOR (HL)\\ AF\>XOR A\\ B0\>OR B\\ B1\>OR C\\ B2\>OR D\\ B3\>OR E\\ B4\>OR H\\ B5\>OR L\\ B6\>OR (HL)\\ B7\>OR A\\ B8\>CP B\\ B9\>CP C\\ BA\>CP D\\ BB\>CP E\\ BC\>CP H\\ BD\>CP L\\ BE\>CP (HL)\\ BF\>CP A\\ C0\>RET NZ\\ C1\>POP BC\\ C2 n n\>JP NZ,(nn)\\ C3 n n\>JP (nn)\\ C4 n n\>CALL NZ,(nn)\\ C5\>PUSH BC\\ C6 n\>ADD A,n\\ C7\>RST 0H\\ C8\>RET Z\\ C9\>RET\\ CA n n\>JP Z,(nn)\\ CB00\>RLC B\\ CB01\>RLC C\\ CB02\>RLC D\\ CB03\>RLC E\\ CB04\>RLC H\\ CB05\>RLC L\\ CB06\>RLC (HL)\\ CB07\>RLC A\\ CB08\>RRC B\\ CB09\>RRC C\\ CB0A\>RRC D\\ CB0B\>RRC E\\ CB0C\>RRC H\\ CB0D\>RRC L\\ CB0E\>RRC (HL)\\ CB0F\>RRC A\\ CB10\>RL B\\ CB11\>RL C\\ CB12\>RL D\\ CB13\>RL E\\ CB14\>RL H\\ CB15\>RL L\\ CB16\>RL (HL)\\ CB17\>RL A\\ CB18\>RR B\\ CB19\>RR C\\ CB1A\>RR D\\ CB1B\>RR E\\ CB1C\>RR H\\ CB1D\>RR L\\ CB1E\>RR (HL)\\ CB1F\>RR A\\ CB20\>SLA B\\ CB21\>SLA C\\ CB22\>SLA D\\ CB23\>SLA E\\ CB24\>SLA H\\ CB25\>SLA L\\ CB26\>SLA (HL)\\ CB27\>SLA A\\ CB28\>SRA B\\ CB29\>SRA C\\ CB2A\>SRA D\\ CB2B\>SRA E\\ CB2C\>SRA H\\ CB2D\>SRA L\\ CB2E\>SRA (HL)\\ CB2F\>SRA A\\ CB30\>SLL B*\\ CB31\>SLL C*\\ CB32\>SLL D*\\ CB33\>SLL E*\\ CB34\>SLL H*\\ CB35\>SLL L*\\ CB36\>SLL (HL)*\\ CB37\>SLL A*\\ CB38\>SRL B\\ CB39\>SRL C\\ CB3A\>SRL D\\ CB3B\>SRL E\\ CB3C\>SRL H\\ CB3D\>SRL L\\ CB3E\>SRL (HL)\\ CB3F\>SRL A\\ CB40\>BIT 0,B\\ CB41\>BIT 0,C\\ CB42\>BIT 0,D\\ CB43\>BIT 0,E\\ CB44\> BIT 0,H\\ CB45\> BIT 0,L\\ CB46\> BIT 0,(HL)\\ CB47\> BIT 0,A\\ CB48\>BIT 1,B\\ CB49\> BIT 1,C\\ CB4A\> BIT 1,D\\ CB4B\> BIT 1,E\\ CB4C\> BIT 1,H\\ CB4D\> BIT 1,L\\ CB4E\> BIT 1,(HL)\\ CB4F\> BIT 1,A\\ CB50\>BIT 2,B\\ CB51\> BIT 2,C\\ CB52\> BIT 2,D\\ CB53\> BIT 2,E\\ CB54\> BIT 2,H\\ CB55\> BIT 2,L\\ CB56\> BIT 2,(HL)\\ CB57\> BIT 2,A\\ CB58\>BIT 3,B\\ CB59\> BIT 3,C\\ CB5A\> BIT 3,D\\ CB5B\> BIT 3,E\\ CB5C\> BIT 3,H\\ CB5D\> BIT 3,L\\ CB5E\> BIT 3,(HL)\\ CB5F\> BIT 3,A\\ CB60\>BIT 4,B\\ CB61\> BIT 4,C\\ CB62\> BIT 4,D\\ CB63\> BIT 4,E\\ CB64\> BIT 4,H\\ CB65\> BIT 4,L\\ CB66\> BIT 4,(HL)\\ CB67\> BIT 4,A\\ CB68\>BIT 5,B\\ CB69\> BIT 5,C\\ CB6A\> BIT 5,D\\ CB6B\> BIT 5,E\\ CB6C\> BIT 5,H\\ CB6D\> BIT 5,L\\ CB6E\> BIT 5,(HL)\\ CB6F\> BIT 5,A\\ CB70\>BIT 6,B\\ CB71\> BIT 6,C\\ CB72\> BIT 6,D\\ CB73\> BIT 6,E\\ CB74\> BIT 6,H\\ CB75\> BIT 6,L\\ CB76\> BIT 6,(HL)\\ CB77\> BIT 6,A\\ CB78\>BIT 7,B\\ CB79\> BIT 7,C\\ CB7A\> BIT 7,D\\ CB7B\> BIT 7,E\\ CB7C\> BIT 7,H\\ CB7D\> BIT 7,L\\ CB7E\> BIT 7,(HL)\\ CB7F\> BIT 7,A\\ CB80\>RES 0,B\\ CB81\>RES 0,C\\ CB82\>RES 0,D\\ CB83\>RES 0,E\\ CB84\> RES 0,H\\ CB85\> RES 0,L\\ CB86\> RES 0,(HL)\\ CB87\> RES 0,A\\ CB88\>RES 1,B\\ CB89\> RES 1,C\\ CB8A\> RES 1,D\\ CB8B\> RES 1,E\\ CB8C\> RES 1,H\\ CB8D\> RES 1,L\\ CB8E\> RES 1,(HL)\\ CB8F\> RES 1,A\\ CB90\>RES 2,B\\ CB91\> RES 2,C\\ CB92\> RES 2,D\\ CB93\> RES 2,E\\ CB94\> RES 2,H\\ CB95\> RES 2,L\\ CB96\> RES 2,(HL)\\ CB97\> RES 2,A\\ CB98\>RES 3,B\\ CB99\> RES 3,C\\ CB9A\> RES 3,D\\ CB9B\> RES 3,E\\ CB9C\> RES 3,H\\ CB9D\> RES 3,L\\ CB9E\> RES 3,(HL)\\ CB9F\> RES 3,A\\ CBA0\>RES 4,B\\ CBA1\> RES 4,C\\ CBA2\> RES 4,D\\ CBA3\> RES 4,E\\ CBA4\> RES 4,H\\ CBA5\> RES 4,L\\ CBA6\> RES 4,(HL)\\ CBA7\> RES 4,A\\ CBA8\>RES 5,B\\ CBA9\> RES 5,C\\ CBAA\> RES 5,D\\ CBAB\> RES 5,E\\ CBAC\> RES 5,H\\ CBAD\> RES 5,L\\ CBAE\> RES 5,(HL)\\ CBAF\> RES 5,A\\ CBB0\>RES 6,B\\ CBB1\> RES 6,C\\ CBB2\> RES 6,D\\ CBB3\> RES 6,E\\ CBB4\> RES 6,H\\ CBB5\> RES 6,L\\ CBB6\> RES 6,(HL)\\ CBB7\> RES 6,A\\ CBB8\>RES 7,B\\ CBB9\> RES 7,C\\ CBBA\> RES 7,D\\ CBBB\> RES 7,E\\ CBBC\> RES 7,H\\ CBBD\> RES 7,L\\ CBBE\> RES 7,(HL)\\ CBBF\> RES 7,A\\ CBC0\>SET 0,B\\ CBC1\>SET 0,C\\ CBC2\>SET 0,D\\ CBC3\>SET 0,E\\ CBC4\> SET 0,H\\ CBC5\> SET 0,L\\ CBC6\> SET 0,(HL)\\ CBC7\> SET 0,A\\ CBC8\>SET 1,B\\ CBC9\> SET 1,C\\ CBCA\> SET 1,D\\ CBCB\> SET 1,E\\ CBCC\> SET 1,H\\ CBCD\> SET 1,L\\ CBCE\> SET 1,(HL)\\ CBCF\> SET 1,A\\ CBD0\>SET 2,B\\ CBD1\> SET 2,C\\ CBD2\> SET 2,D\\ CBD3\> SET 2,E\\ CBD4\> SET 2,H\\ CBD5\> SET 2,L\\ CBD6\> SET 2,(HL)\\ CBD7\> SET 2,A\\ CBD8\>SET 3,B\\ CBD9\> SET 3,C\\ CBDA\> SET 3,D\\ CBDB\> SET 3,E\\ CBDC\> SET 3,H\\ CBDD\> SET 3,L\\ CBDE\> SET 3,(HL)\\ CBDF\> SET 3,A\\ CBE0\>SET 4,B\\ CBE1\> SET 4,C\\ CBE2\> SET 4,D\\ CBE3\> SET 4,E\\ CBE4\> SET 4,H\\ CBE5\> SET 4,L\\ CBE6\> SET 4,(HL)\\ CBE7\> SET 4,A\\ CBE8\>SET 5,B\\ CBE9\> SET 5,C\\ CBEA\> SET 5,D\\ CBEB\> SET 5,E\\ CBEC\> SET 5,H\\ CBED\> SET 5,L\\ CBEE\> SET 5,(HL)\\ CBEF\> SET 5,A\\ CBF0\>SET 6,B\\ CBF1\> SET 6,C\\ CBF2\> SET 6,D\\ CBF3\> SET 6,E\\ CBF4\> SET 6,H\\ CBF5\> SET 6,L\\ CBF6\> SET 6,(HL)\\ CBF7\> SET 6,A\\ CBF8\>SET 7,B\\ CBF9\> SET 7,C\\ CBFA\> SET 7,D\\ CBFB\> SET 7,E\\ CBFC\> SET 7,H\\ CBFD\> SET 7,L\\ CBFE\> SET 7,(HL)\\ CBFF\> SET 7,A\\ CC n n\>CALL Z,(nn)\\ CD n n\>CALL (nn)\\ CE n\>ADC A,n\\ CF\>RST 8H\\ D0\>RET NC\\ D1\>POP DE\\ D2 n n\>JP NC,(nn)\\ D3 n\>OUT (n),A\\ D4 n n\>CALL NC,(nn)\\ D5\>PUSH DE\\ D6 n\>SUB n\\ D7\>RST 10H\\ D8\>RET C\\ D9\>EXX\\ DA n n\>JP C,(nn)\\ DB n\>IN A,(n)\\ DC n n\>CALL C,(nn)\\ DD09\>ADD IX,BC\\ DD19\>ADD IX,DE\\ DD21 n n\>LD IX,nn\\ DD22 n n\>LD (nn),IX\\ DD23\>INC IX\\ DD24\>INC IXh*\\ DD25\>DEC IXh*\\ DD26 n \>LD IXh,n*\\ DD29\>ADD IX,IX\\ DD2A n n\>LD IX,(nn)\\ DD2B\>DEC IX\\ DD2C\>INC IXl*\\ DD2D\>DEC IXl*\\ DD2E n\>LD IXl,n*\\ DD34 d\>INC (IX+d)\\ DD35 d\>DEC (IX+d)\\ DD36 d n\>LD (IX+d),n\\ DD39\>ADD IX,SP\\ DD44\>LD B,IXh*\\ DD45\>LD B,IXl*\\ DD46 d\>LD B,(IX+d)\\ DD4C\>LD C,IXh*\\ DD4D\>LD C,IXl*\\ DD4E d\>LD C,(IX+d)\\ DD54\>LD D,IXh*\\ DD55\>LD D,IXl*\\ DD56 d\>LD D,(IX+d)\\ DD5C\>LD E,IXh*\\ DD5D\>LD E,IXl*\\ DD5E d\>LD E,(IX+d)\\ DD60\>LD IXh,B*\\ DD61\>LD IXh,C*\\ DD62\>LD IXh,D*\\ DD63\>LD IXh,E*\\ DD64\>LD IXh,IXh*\\ DD65\>LD IXh,IXl*\\ DD66 d\>LD H,(IX+d)\\ DD67\>LD IXh,A*\\ DD68\>LD IXl,B*\\ DD69\>LD IXl,C*\\ DD6A\>LD IXl,D*\\ DD6B\>LD IXl,E*\\ DD6C\>LD IXl,IXh*\\ DD6D\>LD IXl,IXl*\\ DD6E d\>LD L,(IX+d)\\ DD6F\>LD IXl,A*\\ DD70 d\>LD (IX+d),B\\ DD71 d\>LD (IX+d),C\\ DD72 d\>LD (IX+d),D\\ DD73 d\>LD (IX+d),E\\ DD74 d\>LD (IX+d),H\\ DD75 d\>LD (IX+d),L\\ DD77 d\>LD (IX+d),A\\ DD7C\>LD A,IXh*\\ DD7D\>LD A,IXl*\\ DD7E d\>LD A,(IX+d)\\ DD84\>ADD A,IXh*\\ DD85\>ADD A,IXl*\\ DD86 d\>ADD A,(IX+d)\\ DD8C\>ADC A,IXh*\\ DD8D\>ADC A,IXl*\\ DD8E d\>ADC A,(IX+d)\\ DD94\>SUB IXh*\\ DD95\>SUB IXl*\\ DD96 d\>SUB (IX+d)\\ DD9C\>SBC A,IXh*\\ DD9D\>SBC A,IXl*\\ DD9E d\>SBC A,(IX+d)\\ DDA4\>AND IXh*\\ DDA5\>AND IXl*\\ DDA6 d\>AND (IX+d)\\ DDAC\>XOR IXh*\\ DDAD\>XOR IXl*\\ DDAE d\>XOR (IX+d)\\ DDB4\>OR IXh*\\ DDB5\>OR IXl*\\ DDB6 d\>OR (IX+d)\\ DDBC\>CP IXh*\\ DDBD\>CP IXl*\\ DDBE d\>CP (IX+d)\\ DDCB d 00\>RLC (IX+d),B*\\ DDCB d 01\>RLC (IX+d),C*\\ DDCB d 02\>RLC (IX+d),D*\\ DDCB d 03\>RLC (IX+d),E*\\ DDCB d 04\>RLC (IX+d),H*\\ DDCB d 05\>RLC (IX+d),L*\\ DDCB d 06\>RLC (IX+d)\\ DDCB d 07\>RLC (IX+d),A*\\ DDCB d 08\>RRC (IX+d),B*\\ DDCB d 09\>RRC (IX+d),C*\\ DDCB d 0A\>RRC (IX+d),D*\\ DDCB d 0B\>RRC (IX+d),E*\\ DDCB d 0C\>RRC (IX+d),H*\\ DDCB d 0D\>RRC (IX+d),L*\\ DDCB d 0E\>RRC (IX+d)\\ DDCB d 0F\>RRC (IX+d),A*\\ DDCB d 10\>RL (IX+d),B*\\ DDCB d 11\>RL (IX+d),C*\\ DDCB d 12\>RL (IX+d),D*\\ DDCB d 13\>RL (IX+d),E*\\ DDCB d 14\>RL (IX+d),H*\\ DDCB d 15\>RL (IX+d),L*\\ DDCB d 16\>RL (IX+d)\\ DDCB d 17\>RL (IX+d),A*\\ DDCB d 18\>RR (IX+d),B*\\ DDCB d 19\>RR (IX+d),C*\\ DDCB d 1A\>RR (IX+d),D*\\ DDCB d 1B\>RR (IX+d),E*\\ DDCB d 1C\>RR (IX+d),H*\\ DDCB d 1D\>RR (IX+d),L*\\ DDCB d 1E\>RR (IX+d)\\ DDCB d 1F\>RR (IX+d),A*\\ DDCB d 20\>SLA (IX+d),B*\\ DDCB d 21\>SLA (IX+d),C*\\ DDCB d 22\>SLA (IX+d),D*\\ DDCB d 23\>SLA (IX+d),E*\\ DDCB d 24\>SLA (IX+d),H*\\ DDCB d 25\>SLA (IX+d),L*\\ DDCB d 26\>SLA (IX+d)\\ DDCB d 27\>SLA (IX+d),A*\\ DDCB d 28\>SRA (IX+d),B*\\ DDCB d 29\>SRA (IX+d),C*\\ DDCB d 2A\>SRA (IX+d),D*\\ DDCB d 2B\>SRA (IX+d),E*\\ DDCB d 2C\>SRA (IX+d),H*\\ DDCB d 2D\>SRA (IX+d),L*\\ DDCB d 2E\>SRA (IX+d)\\ DDCB d 2F\>SRA (IX+d),A*\\ DDCB d 30\>SLL (IX+d),B*\\ DDCB d 31\>SLL (IX+d),C*\\ DDCB d 32\>SLL (IX+d),D*\\ DDCB d 33\>SLL (IX+d),E*\\ DDCB d 34\>SLL (IX+d),H*\\ DDCB d 35\>SLL (IX+d),L*\\ DDCB d 36\>SLL (IX+d)*\\ DDCB d 37\>SLL (IX+d),A*\\ DDCB d 38\>SRL (IX+d),B*\\ DDCB d 39\>SRL (IX+d),C*\\ DDCB d 3A\>SRL (IX+d),D*\\ DDCB d 3B\>SRL (IX+d),E*\\ DDCB d 3C\>SRL (IX+d),H*\\ DDCB d 3D\>SRL (IX+d),L*\\ DDCB d 3E\>SRL (IX+d)\\ DDCB d 3F\>SRL (IX+d),A*\\ DDCB d 40\>BIT 0,(IX+d)*\\ DDCB d 41\>BIT 0,(IX+d)*\\ DDCB d 42\>BIT 0,(IX+d)*\\ DDCB d 43\>BIT 0,(IX+d)*\\ DDCB d 44\>BIT 0,(IX+d)*\\ DDCB d 45\>BIT 0,(IX+d)*\\ DDCB d 46\>BIT 0,(IX+d)\\ DDCB d 47\>BIT 0,(IX+d)*\\ DDCB d 48\>BIT 1,(IX+d)*\\ DDCB d 49\>BIT 1,(IX+d)*\\ DDCB d 4A\>BIT 1,(IX+d)*\\ DDCB d 4B\>BIT 1,(IX+d)*\\ DDCB d 4C\>BIT 1,(IX+d)*\\ DDCB d 4D\>BIT 1,(IX+d)*\\ DDCB d 4E\>BIT 1,(IX+d)\\ DDCB d 4F\>BIT 1,(IX+d)*\\ DDCB d 50\>BIT 2,(IX+d)*\\ DDCB d 51\>BIT 2,(IX+d)*\\ DDCB d 52\>BIT 2,(IX+d)*\\ DDCB d 53\>BIT 2,(IX+d)*\\ DDCB d 54\>BIT 2,(IX+d)*\\ DDCB d 55\>BIT 2,(IX+d)*\\ DDCB d 56\>BIT 2,(IX+d)\\ DDCB d 57\>BIT 2,(IX+d)*\\ DDCB d 58\>BIT 3,(IX+d)*\\ DDCB d 59\>BIT 3,(IX+d)*\\ DDCB d 5A\>BIT 3,(IX+d)*\\ DDCB d 5B\>BIT 3,(IX+d)*\\ DDCB d 5C\>BIT 3,(IX+d)*\\ DDCB d 5D\>BIT 3,(IX+d)*\\ DDCB d 5E\>BIT 3,(IX+d)\\ DDCB d 5F\>BIT 3,(IX+d)*\\ DDCB d 60\>BIT 4,(IX+d)*\\ DDCB d 61\>BIT 4,(IX+d)*\\ DDCB d 62\>BIT 4,(IX+d)*\\ DDCB d 63\>BIT 4,(IX+d)*\\ DDCB d 64\>BIT 4,(IX+d)*\\ DDCB d 65\>BIT 4,(IX+d)*\\ DDCB d 66\>BIT 4,(IX+d)\\ DDCB d 67\>BIT 4,(IX+d)*\\ DDCB d 68\>BIT 5,(IX+d)*\\ DDCB d 69\>BIT 5,(IX+d)*\\ DDCB d 6A\>BIT 5,(IX+d)*\\ DDCB d 6B\>BIT 5,(IX+d)*\\ DDCB d 6C\>BIT 5,(IX+d)*\\ DDCB d 6D\>BIT 5,(IX+d)*\\ DDCB d 6E\>BIT 5,(IX+d)\\ DDCB d 6F\>BIT 5,(IX+d)*\\ DDCB d 70\>BIT 6,(IX+d)*\\ DDCB d 71\>BIT 6,(IX+d)*\\ DDCB d 72\>BIT 6,(IX+d)*\\ DDCB d 73\>BIT 6,(IX+d)*\\ DDCB d 74\>BIT 6,(IX+d)*\\ DDCB d 75\>BIT 6,(IX+d)*\\ DDCB d 76\>BIT 6,(IX+d)\\ DDCB d 77\>BIT 6,(IX+d)*\\ DDCB d 78\>BIT 7,(IX+d)*\\ DDCB d 79\>BIT 7,(IX+d)*\\ DDCB d 7A\>BIT 7,(IX+d)*\\ DDCB d 7B\>BIT 7,(IX+d)*\\ DDCB d 7C\>BIT 7,(IX+d)*\\ DDCB d 7D\>BIT 7,(IX+d)*\\ DDCB d 7E\>BIT 7,(IX+d)\\ DDCB d 7F\>BIT 7,(IX+d)*\\ DDCB d 80\>RES 0,(IX+d),B*\\ DDCB d 81\>RES 0,(IX+d),C*\\ DDCB d 82\>RES 0,(IX+d),D*\\ DDCB d 83\>RES 0,(IX+d),E*\\ DDCB d 84\>RES 0,(IX+d),H*\\ DDCB d 85\>RES 0,(IX+d),L*\\ DDCB d 86\>RES 0,(IX+d)\\ DDCB d 87\>RES 0,(IX+d),A*\\ DDCB d 88\>RES 1,(IX+d),B*\\ DDCB d 89\>RES 1,(IX+d),C*\\ DDCB d 8A\>RES 1,(IX+d),D*\\ DDCB d 8B\>RES 1,(IX+d),E*\\ DDCB d 8C\>RES 1,(IX+d),H*\\ DDCB d 8D\>RES 1,(IX+d),L*\\ DDCB d 8E\>RES 1,(IX+d)\\ DDCB d 8F\>RES 1,(IX+d),A*\\ DDCB d 90\>RES 2,(IX+d),B*\\ DDCB d 91\>RES 2,(IX+d),C*\\ DDCB d 92\>RES 2,(IX+d),D*\\ DDCB d 93\>RES 2,(IX+d),E*\\ DDCB d 94\>RES 2,(IX+d),H*\\ DDCB d 95\>RES 2,(IX+d),L*\\ DDCB d 96\>RES 2,(IX+d)\\ DDCB d 97\>RES 2,(IX+d),A*\\ DDCB d 98\>RES 3,(IX+d),B*\\ DDCB d 99\>RES 3,(IX+d),C*\\ DDCB d 9A\>RES 3,(IX+d),D*\\ DDCB d 9B\>RES 3,(IX+d),E*\\ DDCB d 9C\>RES 3,(IX+d),H*\\ DDCB d 9D\>RES 3,(IX+d),L*\\ DDCB d 9E\>RES 3,(IX+d)\\ DDCB d 9F\>RES 3,(IX+d),A*\\ DDCB d A0\>RES 4,(IX+d),B*\\ DDCB d A1\>RES 4,(IX+d),C*\\ DDCB d A2\>RES 4,(IX+d),D*\\ DDCB d A3\>RES 4,(IX+d),E*\\ DDCB d A4\>RES 4,(IX+d),H*\\ DDCB d A5\>RES 4,(IX+d),L*\\ DDCB d A6\>RES 4,(IX+d)\\ DDCB d A7\>RES 4,(IX+d),A*\\ DDCB d A8\>RES 5,(IX+d),B*\\ DDCB d A9\>RES 5,(IX+d),C*\\ DDCB d AA\>RES 5,(IX+d),D*\\ DDCB d AB\>RES 5,(IX+d),E*\\ DDCB d AC\>RES 5,(IX+d),H*\\ DDCB d AD\>RES 5,(IX+d),L*\\ DDCB d AE\>RES 5,(IX+d)\\ DDCB d AF\>RES 5,(IX+d),A*\\ DDCB d B0\>RES 6,(IX+d),B*\\ DDCB d B1\>RES 6,(IX+d),C*\\ DDCB d B2\>RES 6,(IX+d),D*\\ DDCB d B3\>RES 6,(IX+d),E*\\ DDCB d B4\>RES 6,(IX+d),H*\\ DDCB d B5\>RES 6,(IX+d),L*\\ DDCB d B6\>RES 6,(IX+d)\\ DDCB d B7\>RES 6,(IX+d),A*\\ DDCB d B8\>RES 7,(IX+d),B*\\ DDCB d B9\>RES 7,(IX+d),C*\\ DDCB d BA\>RES 7,(IX+d),D*\\ DDCB d BB\>RES 7,(IX+d),E*\\ DDCB d BC\>RES 7,(IX+d),H*\\ DDCB d BD\>RES 7,(IX+d),L*\\ DDCB d BE\>RES 7,(IX+d)\\ DDCB d BF\>RES 7,(IX+d),A*\\ DDCB d C0\>SET 0,(IX+d),B*\\ DDCB d C1\>SET 0,(IX+d),C*\\ DDCB d C2\>SET 0,(IX+d),D*\\ DDCB d C3\>SET 0,(IX+d),E*\\ DDCB d C4\>SET 0,(IX+d),H*\\ DDCB d C5\>SET 0,(IX+d),L*\\ DDCB d C6\>SET 0,(IX+d)\\ DDCB d C7\>SET 0,(IX+d),A*\\ DDCB d C8\>SET 1,(IX+d),B*\\ DDCB d C9\>SET 1,(IX+d),C*\\ DDCB d CA\>SET 1,(IX+d),D*\\ DDCB d CB\>SET 1,(IX+d),E*\\ DDCB d CC\>SET 1,(IX+d),H*\\ DDCB d CD\>SET 1,(IX+d),L*\\ DDCB d CE\>SET 1,(IX+d)\\ DDCB d CF\>SET 1,(IX+d),A*\\ DDCB d D0\>SET 2,(IX+d),B*\\ DDCB d D1\>SET 2,(IX+d),C*\\ DDCB d D2\>SET 2,(IX+d),D*\\ DDCB d D3\>SET 2,(IX+d),E*\\ DDCB d D4\>SET 2,(IX+d),H*\\ DDCB d D5\>SET 2,(IX+d),L*\\ DDCB d D6\>SET 2,(IX+d)\\ DDCB d D7\>SET 2,(IX+d),A*\\ DDCB d D8\>SET 3,(IX+d),B*\\ DDCB d D9\>SET 3,(IX+d),C*\\ DDCB d DA\>SET 3,(IX+d),D*\\ DDCB d DB\>SET 3,(IX+d),E*\\ DDCB d DC\>SET 3,(IX+d),H*\\ DDCB d DD\>SET 3,(IX+d),L*\\ DDCB d DE\>SET 3,(IX+d)\\ DDCB d DF\>SET 3,(IX+d),A*\\ DDCB d E0\>SET 4,(IX+d),B*\\ DDCB d E1\>SET 4,(IX+d),C*\\ DDCB d E2\>SET 4,(IX+d),D*\\ DDCB d E3\>SET 4,(IX+d),E*\\ DDCB d E4\>SET 4,(IX+d),H*\\ DDCB d E5\>SET 4,(IX+d),L*\\ DDCB d E6\>SET 4,(IX+d)\\ DDCB d E7\>SET 4,(IX+d),A*\\ DDCB d E8\>SET 5,(IX+d),B*\\ DDCB d E9\>SET 5,(IX+d),C*\\ DDCB d EA\>SET 5,(IX+d),D*\\ DDCB d EB\>SET 5,(IX+d),E*\\ DDCB d EC\>SET 5,(IX+d),H*\\ DDCB d ED\>SET 5,(IX+d),L*\\ DDCB d EE\>SET 5,(IX+d)\\ DDCB d EF\>SET 5,(IX+d),A*\\ DDCB d F0\>SET 6,(IX+d),B*\\ DDCB d F1\>SET 6,(IX+d),C*\\ DDCB d F2\>SET 6,(IX+d),D*\\ DDCB d F3\>SET 6,(IX+d),E*\\ DDCB d F4\>SET 6,(IX+d),H*\\ DDCB d F5\>SET 6,(IX+d),L*\\ DDCB d F6\>SET 6,(IX+d)\\ DDCB d F7\>SET 6,(IX+d),A*\\ DDCB d F8\>SET 7,(IX+d),B*\\ DDCB d F9\>SET 7,(IX+d),C*\\ DDCB d FA\>SET 7,(IX+d),D*\\ DDCB d FB\>SET 7,(IX+d),E*\\ DDCB d FC\>SET 7,(IX+d),H*\\ DDCB d FD\>SET 7,(IX+d),L*\\ DDCB d FE\>SET 7,(IX+d)\\ DDCB d FF\>SET 7,(IX+d),A*\\ DDE1\>POP IX\\ DDE3\>EX (SP),IX\\ DDE5\>PUSH IX\\ DDE9\>JP (IX)\\ DDF9\>LD SP,IX\\ DE n\>SBC A,n\\ DF\>RST 18H\\ E0\>RET PO\\ E1\>POP HL\\ E2 n n\>JP PO,(nn)\\ E3\>EX (SP),HL\\ E4 n n\>CALL PO,(nn)\\ E5\>PUSH HL\\ E6 n\>AND n\\ E7\>RST 20H\\ E8\>RET PE\\ E9\>JP (HL)\\ EA n n\>JP PE,(nn)\\ EB\>EX DE,HL\\ EC n n\>CALL PE,(nn)\\ ED40\>IN B,(C)\\ ED41\>OUT (C),B\\ ED42\>SBC HL,BC\\ ED43 n n\>LD (nn),BC\\ ED44\>NEG\\ ED45\>RETN\\ ED46\>IM 0\\ ED47\>LD I,A\\ ED48\>IN C,(C)\\ ED49\>OUT (C),C\\ ED4A\>ADC HL,BC\\ ED4B n n\>LD BC,(nn)\\ ED4C\>NEG*\\ ED4D\>RETI\\ ED4E\>IM 0*\\ ED4F\>LD R,A\\ ED50\>IN D,(C)\\ ED51\>OUT (C),D\\ ED52\>SBC HL,DE\\ ED53 n n\>LD (nn),DE\\ ED54\>NEG*\\ ED55\>RETN*\\ ED56\>IM 1\\ ED57\>LD A,I\\ ED58\>IN E,(C)\\ ED59\>OUT (C),E\\ ED5A\>ADC HL,DE\\ ED5B n n\>LD DE,(nn)\\ ED5C\>NEG*\\ ED5D\>RETN*\\ ED5E\>IM 2\\ ED5F\>LD A,R\\ ED60\>IN H,(C)\\ ED61\>OUT (C),H\\ ED62\>SBC HL,HL\\ ED63 n n\>LD (nn),HL\\ ED64\>NEG*\\ ED65\>RETN*\\ ED66\>IM 0*\\ ED67\>RRD\\ ED68\>IN L,(C)\\ ED69\>OUT (C),L\\ ED6A\>ADC HL,HL\\ ED6B n n\>LD HL,(nn)\\ ED6C\>NEG*\\ ED6D\>RETN*\\ ED6E\>IM 0*\\ ED6F\>RLD\\ ED70\>IN F,(C)* / IN (C)*\\ ED71\>OUT (C),0*\\ ED72\>SBC HL,SP\\ ED73 n n\>LD (nn),SP\\ ED74\>NEG*\\ ED75\>RETN*\\ ED76\>IM 1*\\ ED78\>IN A,(C)\\ ED79\>OUT (C),A\\ ED7A\>ADC HL,SP\\ ED7B n n\>LD SP,(nn)\\ ED7C\>NEG*\\ ED7D\>RETN*\\ ED7E\>IM 2*\\ EDA0\>LDI\\ EDA1\>CPI\\ EDA2\>INI\\ EDA3\>OUTI\\ EDA8\>LDD\\ EDA9\>CPD\\ EDAA\>IND\\ EDAB\>OUTD\\ EDB0\>LDIR\\ EDB1\>CPIR\\ EDB2\>INIR\\ EDB3\>OTIR\\ EDB8\>LDDR\\ EDB9\>CPDR\\ EDBA\>INDR\\ EDBB\>OTDR\\ EE n\>XOR n\\ EF\>RST 28H\\ F0\>RET P\\ F1\>POP AF\\ F2 n n\>JP P,(nn)\\ F3\>DI\\ F4 n n\>CALL P,(nn)\\ F5\>PUSH AF\\ F6 n\>OR n\\ F7\>RST 30H\\ F8\>RET M\\ F9\>LD SP,HL\\ FA n n\>JP M,(nn)\\ FB\>EI\\ FC n n\>CALL M,(nn)\\ FD09\>ADD IY,BC\\ FD19\>ADD IY,DE\\ FD21 n n\>LD IY,nn\\ FD22 n n\>LD (nn),IY\\ FD23\>INC IY\\ FD24\>INC IYh*\\ FD25\>DEC IYh*\\ FD26 n\>LD IYh,n*\\ FD29\>ADD IY,IY\\ FD2A n n\>LD IY,(nn)\\ FD2B\>DEC IY\\ FD2C\>INC IYl*\\ FD2D\>DEC IYl*\\ FD2E n\>LD IYl,n*\\ FD34 d\>INC (IY+d)\\ FD35 d\>DEC (IY+d)\\ FD36 d n\>LD (IY+d),n\\ FD39\>ADD IY,SP\\ FD44\>LD B,IYh*\\ FD45\>LD B,IYl*\\ FD46 d\>LD B,(IY+d)\\ FD4C\>LD C,IYh*\\ FD4D\>LD C,IYl*\\ FD4E d\>LD C,(IY+d)\\ FD54\>LD D,IYh*\\ FD55\>LD D,IYl*\\ FD56 d\>LD D,(IY+d)\\ FD5C\>LD E,IYh*\\ FD5D\>LD E,IYl*\\ FD5E d\>LD E,(IY+d)\\ FD60\>LD IYh,B*\\ FD61\>LD IYh,C*\\ FD62\>LD IYh,D*\\ FD63\>LD IYh,E*\\ FD64\>LD IYh,IYh*\\ FD65\>LD IYh,IYl*\\ FD66 d\>LD H,(IY+d)\\ FD67\>LD IYh,A*\\ FD68\>LD IYl,B*\\ FD69\>LD IYl,C*\\ FD6A\>LD IYl,D*\\ FD6B\>LD IYl,E*\\ FD6C\>LD IYl,IYh*\\ FD6D\>LD IYl,IYl*\\ FD6E d\>LD L,(IY+d)\\ FD6F\>LD IYl,A*\\ FD70 d\>LD (IY+d),B\\ FD71 d\>LD (IY+d),C\\ FD72 d\>LD (IY+d),D\\ FD73 d\>LD (IY+d),E\\ FD74 d\>LD (IY+d),H\\ FD75 d\>LD (IY+d),L\\ FD77 d\>LD (IY+d),A\\ FD7C\>LD A,IYh*\\ FD7D\>LD A,IYl*\\ FD7E d\>LD A,(IY+d)\\ FD84\>ADD A,IYh*\\ FD85\>ADD A,IYl*\\ FD86 d\>ADD A,(IY+d)\\ FD8C\>ADC A,IYh*\\ FD8D\>ADC A,IYl*\\ FD8E d\>ADC A,(IY+d)\\ FD94\>SUB IYh*\\ FD95\>SUB IYl*\\ FD96 d\>SUB (IY+d)\\ FD9C\>SBC A,IYh*\\ FD9D\>SBC A,IYl*\\ FD9E d\>SBC A,(IY+d)\\ FDA4\>AND IYh*\\ FDA5\>AND IYl*\\ FDA6 d\>AND (IY+d)\\ FDAC\>XOR IYh*\\ FDAD\>XOR IYl*\\ FDAE d\>XOR (IY+d)\\ FDB4\>OR IYh*\\ FDB5\>OR IYl*\\ FDB6 d\>OR (IY+d)\\ FDBC\>CP IYh*\\ FDBD\>CP IYl*\\ FDBE d\>CP (IY+d)\\ FDCB d 00\>RLC (IY+d),B*\\ FDCB d 01\>RLC (IY+d),C*\\ FDCB d 02\>RLC (IY+d),D*\\ FDCB d 03\>RLC (IY+d),E*\\ FDCB d 04\>RLC (IY+d),H*\\ FDCB d 05\>RLC (IY+d),L*\\ FDCB d 06\>RLC (IY+d)\\ FDCB d 07\>RLC (IY+d),A*\\ FDCB d 08\>RRC (IY+d),B*\\ FDCB d 09\>RRC (IY+d),C*\\ FDCB d 0A\>RRC (IY+d),D*\\ FDCB d 0B\>RRC (IY+d),E*\\ FDCB d 0C\>RRC (IY+d),H*\\ FDCB d 0D\>RRC (IY+d),L*\\ FDCB d 0E\>RRC (IY+d)\\ FDCB d 0F\>RRC (IY+d),A*\\ FDCB d 10\>RL (IY+d),B*\\ FDCB d 11\>RL (IY+d),C*\\ FDCB d 12\>RL (IY+d),D*\\ FDCB d 13\>RL (IY+d),E*\\ FDCB d 14\>RL (IY+d),H*\\ FDCB d 15\>RL (IY+d),L*\\ FDCB d 16\>RL (IY+d)\\ FDCB d 17\>RL (IY+d),A*\\ FDCB d 18\>RR (IY+d),B*\\ FDCB d 19\>RR (IY+d),C*\\ FDCB d 1A\>RR (IY+d),D*\\ FDCB d 1B\>RR (IY+d),E*\\ FDCB d 1C\>RR (IY+d),H*\\ FDCB d 1D\>RR (IY+d),L*\\ FDCB d 1E\>RR (IY+d)\\ FDCB d 1F\>RR (IY+d),A*\\ FDCB d 20\>SLA (IY+d),B*\\ FDCB d 21\>SLA (IY+d),C*\\ FDCB d 22\>SLA (IY+d),D*\\ FDCB d 23\>SLA (IY+d),E*\\ FDCB d 24\>SLA (IY+d),H*\\ FDCB d 25\>SLA (IY+d),L*\\ FDCB d 26\>SLA (IY+d)\\ FDCB d 27\>SLA (IY+d),A*\\ FDCB d 28\>SRA (IY+d),B*\\ FDCB d 29\>SRA (IY+d),C*\\ FDCB d 2A\>SRA (IY+d),D*\\ FDCB d 2B\>SRA (IY+d),E*\\ FDCB d 2C\>SRA (IY+d),H*\\ FDCB d 2D\>SRA (IY+d),L*\\ FDCB d 2E\>SRA (IY+d)\\ FDCB d 2F\>SRA (IY+d),A*\\ FDCB d 30\>SLL (IY+d),B*\\ FDCB d 31\>SLL (IY+d),C*\\ FDCB d 32\>SLL (IY+d),D*\\ FDCB d 33\>SLL (IY+d),E*\\ FDCB d 34\>SLL (IY+d),H*\\ FDCB d 35\>SLL (IY+d),L*\\ FDCB d 36\>SLL (IY+d)*\\ FDCB d 37\>SLL (IY+d),A*\\ FDCB d 38\>SRL (IY+d),B*\\ FDCB d 39\>SRL (IY+d),C*\\ FDCB d 3A\>SRL (IY+d),D*\\ FDCB d 3B\>SRL (IY+d),E*\\ FDCB d 3C\>SRL (IY+d),H*\\ FDCB d 3D\>SRL (IY+d),L*\\ FDCB d 3E\>SRL (IY+d)\\ FDCB d 3F\>SRL (IY+d),A*\\ FDCB d 40\>BIT 0,(IY+d)*\\ FDCB d 41\>BIT 0,(IY+d)*\\ FDCB d 42\>BIT 0,(IY+d)*\\ FDCB d 43\>BIT 0,(IY+d)*\\ FDCB d 44\>BIT 0,(IY+d)*\\ FDCB d 45\>BIT 0,(IY+d)*\\ FDCB d 46\>BIT 0,(IY+d)\\ FDCB d 47\>BIT 0,(IY+d)*\\ FDCB d 48\>BIT 1,(IY+d)*\\ FDCB d 49\>BIT 1,(IY+d)*\\ FDCB d 4A\>BIT 1,(IY+d)*\\ FDCB d 4B\>BIT 1,(IY+d)*\\ FDCB d 4C\>BIT 1,(IY+d)*\\ FDCB d 4D\>BIT 1,(IY+d)*\\ FDCB d 4E\>BIT 1,(IY+d)\\ FDCB d 4F\>BIT 1,(IY+d)*\\ FDCB d 50\>BIT 2,(IY+d)*\\ FDCB d 51\>BIT 2,(IY+d)*\\ FDCB d 52\>BIT 2,(IY+d)*\\ FDCB d 53\>BIT 2,(IY+d)*\\ FDCB d 54\>BIT 2,(IY+d)*\\ FDCB d 55\>BIT 2,(IY+d)*\\ FDCB d 56\>BIT 2,(IY+d)\\ FDCB d 57\>BIT 2,(IY+d)*\\ FDCB d 58\>BIT 3,(IY+d)*\\ FDCB d 59\>BIT 3,(IY+d)*\\ FDCB d 5A\>BIT 3,(IY+d)*\\ FDCB d 5B\>BIT 3,(IY+d)*\\ FDCB d 5C\>BIT 3,(IY+d)*\\ FDCB d 5D\>BIT 3,(IY+d)*\\ FDCB d 5E\>BIT 3,(IY+d)\\ FDCB d 5F\>BIT 3,(IY+d)*\\ FDCB d 60\>BIT 4,(IY+d)*\\ FDCB d 61\>BIT 4,(IY+d)*\\ FDCB d 62\>BIT 4,(IY+d)*\\ FDCB d 63\>BIT 4,(IY+d)*\\ FDCB d 64\>BIT 4,(IY+d)*\\ FDCB d 65\>BIT 4,(IY+d)*\\ FDCB d 66\>BIT 4,(IY+d)\\ FDCB d 67\>BIT 4,(IY+d)*\\ FDCB d 68\>BIT 5,(IY+d)*\\ FDCB d 69\>BIT 5,(IY+d)*\\ FDCB d 6A\>BIT 5,(IY+d)*\\ FDCB d 6B\>BIT 5,(IY+d)*\\ FDCB d 6C\>BIT 5,(IY+d)*\\ FDCB d 6D\>BIT 5,(IY+d)*\\ FDCB d 6E\>BIT 5,(IY+d)\\ FDCB d 6F\>BIT 5,(IY+d)*\\ FDCB d 70\>BIT 6,(IY+d)*\\ FDCB d 71\>BIT 6,(IY+d)*\\ FDCB d 72\>BIT 6,(IY+d)*\\ FDCB d 73\>BIT 6,(IY+d)*\\ FDCB d 74\>BIT 6,(IY+d)*\\ FDCB d 75\>BIT 6,(IY+d)*\\ FDCB d 76\>BIT 6,(IY+d)\\ FDCB d 77\>BIT 6,(IY+d)*\\ FDCB d 78\>BIT 7,(IY+d)*\\ FDCB d 79\>BIT 7,(IY+d)*\\ FDCB d 7A\>BIT 7,(IY+d)*\\ FDCB d 7B\>BIT 7,(IY+d)*\\ FDCB d 7C\>BIT 7,(IY+d)*\\ FDCB d 7D\>BIT 7,(IY+d)*\\ FDCB d 7E\>BIT 7,(IY+d)\\ FDCB d 7F\>BIT 7,(IY+d)*\\ FDCB d 80\>RES 0,(IY+d),B*\\ FDCB d 81\>RES 0,(IY+d),C*\\ FDCB d 82\>RES 0,(IY+d),D*\\ FDCB d 83\>RES 0,(IY+d),E*\\ FDCB d 84\>RES 0,(IY+d),H*\\ FDCB d 85\>RES 0,(IY+d),L*\\ FDCB d 86\>RES 0,(IY+d)\\ FDCB d 87\>RES 0,(IY+d),A*\\ FDCB d 88\>RES 1,(IY+d),B*\\ FDCB d 89\>RES 1,(IY+d),C*\\ FDCB d 8A\>RES 1,(IY+d),D*\\ FDCB d 8B\>RES 1,(IY+d),E*\\ FDCB d 8C\>RES 1,(IY+d),H*\\ FDCB d 8D\>RES 1,(IY+d),L*\\ FDCB d 8E\>RES 1,(IY+d)\\ FDCB d 8F\>RES 1,(IY+d),A*\\ FDCB d 90\>RES 2,(IY+d),B*\\ FDCB d 91\>RES 2,(IY+d),C*\\ FDCB d 92\>RES 2,(IY+d),D*\\ FDCB d 93\>RES 2,(IY+d),E*\\ FDCB d 94\>RES 2,(IY+d),H*\\ FDCB d 95\>RES 2,(IY+d),L*\\ FDCB d 96\>RES 2,(IY+d)\\ FDCB d 97\>RES 2,(IY+d),A*\\ FDCB d 98\>RES 3,(IY+d),B*\\ FDCB d 99\>RES 3,(IY+d),C*\\ FDCB d 9A\>RES 3,(IY+d),D*\\ FDCB d 9B\>RES 3,(IY+d),E*\\ FDCB d 9C\>RES 3,(IY+d),H*\\ FDCB d 9D\>RES 3,(IY+d),L*\\ FDCB d 9E\>RES 3,(IY+d)\\ FDCB d 9F\>RES 3,(IY+d),A*\\ FDCB d A0\>RES 4,(IY+d),B*\\ FDCB d A1\>RES 4,(IY+d),C*\\ FDCB d A2\>RES 4,(IY+d),D*\\ FDCB d A3\>RES 4,(IY+d),E*\\ FDCB d A4\>RES 4,(IY+d),H*\\ FDCB d A5\>RES 4,(IY+d),L*\\ FDCB d A6\>RES 4,(IY+d)\\ FDCB d A7\>RES 4,(IY+d),A*\\ FDCB d A8\>RES 5,(IY+d),B*\\ FDCB d A9\>RES 5,(IY+d),C*\\ FDCB d AA\>RES 5,(IY+d),D*\\ FDCB d AB\>RES 5,(IY+d),E*\\ FDCB d AC\>RES 5,(IY+d),H*\\ FDCB d AD\>RES 5,(IY+d),L*\\ FDCB d AE\>RES 5,(IY+d)\\ FDCB d AF\>RES 5,(IY+d),A*\\ FDCB d B0\>RES 6,(IY+d),B*\\ FDCB d B1\>RES 6,(IY+d),C*\\ FDCB d B2\>RES 6,(IY+d),D*\\ FDCB d B3\>RES 6,(IY+d),E*\\ FDCB d B4\>RES 6,(IY+d),H*\\ FDCB d B5\>RES 6,(IY+d),L*\\ FDCB d B6\>RES 6,(IY+d)\\ FDCB d B7\>RES 6,(IY+d),A*\\ FDCB d B8\>RES 7,(IY+d),B*\\ FDCB d B9\>RES 7,(IY+d),C*\\ FDCB d BA\>RES 7,(IY+d),D*\\ FDCB d BB\>RES 7,(IY+d),E*\\ FDCB d BC\>RES 7,(IY+d),H*\\ FDCB d BD\>RES 7,(IY+d),L*\\ FDCB d BE\>RES 7,(IY+d)\\ FDCB d BF\>RES 7,(IY+d),A*\\ FDCB d C0\>SET 0,(IY+d),B*\\ FDCB d C1\>SET 0,(IY+d),C*\\ FDCB d C2\>SET 0,(IY+d),D*\\ FDCB d C3\>SET 0,(IY+d),E*\\ FDCB d C4\>SET 0,(IY+d),H*\\ FDCB d C5\>SET 0,(IY+d),L*\\ FDCB d C6\>SET 0,(IY+d)\\ FDCB d C7\>SET 0,(IY+d),A*\\ FDCB d C8\>SET 1,(IY+d),B*\\ FDCB d C9\>SET 1,(IY+d),C*\\ FDCB d CA\>SET 1,(IY+d),D*\\ FDCB d CB\>SET 1,(IY+d),E*\\ FDCB d CC\>SET 1,(IY+d),H*\\ FDCB d CD\>SET 1,(IY+d),L*\\ FDCB d CE\>SET 1,(IY+d)\\ FDCB d CF\>SET 1,(IY+d),A*\\ FDCB d D0\>SET 2,(IY+d),B*\\ FDCB d D1\>SET 2,(IY+d),C*\\ FDCB d D2\>SET 2,(IY+d),D*\\ FDCB d D3\>SET 2,(IY+d),E*\\ FDCB d D4\>SET 2,(IY+d),H*\\ FDCB d D5\>SET 2,(IY+d),L*\\ FDCB d D6\>SET 2,(IY+d)\\ FDCB d D7\>SET 2,(IY+d),A*\\ FDCB d D8\>SET 3,(IY+d),B*\\ FDCB d D9\>SET 3,(IY+d),C*\\ FDCB d DA\>SET 3,(IY+d),D*\\ FDCB d DB\>SET 3,(IY+d),E*\\ FDCB d DC\>SET 3,(IY+d),H*\\ FDCB d DD\>SET 3,(IY+d),L*\\ FDCB d DE\>SET 3,(IY+d)\\ FDCB d DF\>SET 3,(IY+d),A*\\ FDCB d E0\>SET 4,(IY+d),B*\\ FDCB d E1\>SET 4,(IY+d),C*\\ FDCB d E2\>SET 4,(IY+d),D*\\ FDCB d E3\>SET 4,(IY+d),E*\\ FDCB d E4\>SET 4,(IY+d),H*\\ FDCB d E5\>SET 4,(IY+d),L*\\ FDCB d E6\>SET 4,(IY+d)\\ FDCB d E7\>SET 4,(IY+d),A*\\ FDCB d E8\>SET 5,(IY+d),B*\\ FDCB d E9\>SET 5,(IY+d),C*\\ FDCB d EA\>SET 5,(IY+d),D*\\ FDCB d EB\>SET 5,(IY+d),E*\\ FDCB d EC\>SET 5,(IY+d),H*\\ FDCB d ED\>SET 5,(IY+d),L*\\ FDCB d EE\>SET 5,(IY+d)\\ FDCB d EF\>SET 5,(IY+d),A*\\ FDCB d F0\>SET 6,(IY+d),B*\\ FDCB d F1\>SET 6,(IY+d),C*\\ FDCB d F2\>SET 6,(IY+d),D*\\ FDCB d F3\>SET 6,(IY+d),E*\\ FDCB d F4\>SET 6,(IY+d),H*\\ FDCB d F5\>SET 6,(IY+d),L*\\ FDCB d F6\>SET 6,(IY+d)\\ FDCB d F7\>SET 6,(IY+d),A*\\ FDCB d F8\>SET 7,(IY+d),B*\\ FDCB d F9\>SET 7,(IY+d),C*\\ FDCB d FA\>SET 7,(IY+d),D*\\ FDCB d FB\>SET 7,(IY+d),E*\\ FDCB d FC\>SET 7,(IY+d),H*\\ FDCB d FD\>SET 7,(IY+d),L*\\ FDCB d FE\>SET 7,(IY+d)\\ FDCB d FF\>SET 7,(IY+d),A*\\ FDE1\>POP IY\\ FDE3\>EX (SP),IY\\ FDE5\>PUSH IY\\ FDE9\>JP (IY)\\ FDF9\>LD SP,IY\\ FE n\>CP n\\ FF\>RST 38H \end{tabbing} } \end{multicols} \normalsize \chapter{GNU Free Documentation License} \label{gfdl} Version 1.1, March 2000\\ Copyright \copyright\ 2000 Free Software Foundation, Inc.\\ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\\ Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. \section*{Preamble} The purpose of this License is to make a manual, textbook, or other written document ``free'' in the sense of freedom: to assure everyone the effective freedom to copy and redistribute it, with or without modifying it, either commercially or noncommercially. Secondarily, this License preserves for the author and publisher a way to get credit for their work, while not being considered responsible for modifications made by others. This License is a kind of ``copyleft'', which means that derivative works of the document must themselves be free in the same sense. It complements the GNU General Public License, which is a copyleft license designed for free software. We have designed this License in order to use it for manuals for free software, because free software needs free documentation: a free program should come with manuals providing the same freedoms that the software does. But this License is not limited to software manuals; it can be used for any textual work, regardless of subject matter or whether it is published as a printed book. We recommend this License principally for works whose purpose is instruction or reference. \section{Applicability and Definitions} This License applies to any manual or other work that contains a notice placed by the copyright holder saying it can be distributed under the terms of this License. The ``Document'', below, refers to any such manual or work. Any member of the public is a licensee, and is addressed as ``you''. A ``Modified Version'' of the Document means any work containing the Document or a portion of it, either copied verbatim, or with modifications and/or translated into another language. A ``Secondary Section'' is a named appendix or a front-matter section of the Document that deals exclusively with the relationship of the publishers or authors of the Document to the Document's overall subject (or to related matters) and contains nothing that could fall directly within that overall subject. (For example, if the Document is in part a textbook of mathematics, a Secondary Section may not explain any mathematics.) The relationship could be a matter of historical connection with the subject or with related matters, or of legal, commercial, philosophical, ethical or political position regarding them. The ``Invariant Sections'' are certain Secondary Sections whose titles are designated, as being those of Invariant Sections, in the notice that says that the Document is released under this License. The ``Cover Texts'' are certain short passages of text that are listed, as Front-Cover Texts or Back-Cover Texts, in the notice that says that the Document is released under this License. A ``Transparent'' copy of the Document means a machine-readable copy, represented in a format whose specification is available to the general public, whose contents can be viewed and edited directly and straightforwardly with generic text editors or (for images composed of pixels) generic paint programs or (for drawings) some widely available drawing editor, and that is suitable for input to text formatters or for automatic translation to a variety of formats suitable for input to text formatters. A copy made in an otherwise Transparent file format whose markup has been designed to thwart or discourage subsequent modification by readers is not Transparent. A copy that is not ``Transparent'' is called ``Opaque''. Examples of suitable formats for Transparent copies include plain ASCII without markup, Texinfo input format, \LaTeX~input format, SGML or XML using a publicly available DTD, and standard-conforming simple HTML designed for human modification. Opaque formats include PostScript, PDF, proprietary formats that can be read and edited only by proprietary word processors, SGML or XML for which the DTD and/or processing tools are not generally available, and the machine-generated HTML produced by some word processors for output purposes only. The ``Title Page'' means, for a printed book, the title page itself, plus such following pages as are needed to hold, legibly, the material this License requires to appear in the title page. For works in formats which do not have any title page as such, ``Title Page'' means the text near the most prominent appearance of the work's title, preceding the beginning of the body of the text. \section{Verbatim Copying} You may copy and distribute the Document in any medium, either commercially or noncommercially, provided that this License, the copyright notices, and the license notice saying this License applies to the Document are reproduced in all copies, and that you add no other conditions whatsoever to those of this License. You may not use technical measures to obstruct or control the reading or further copying of the copies you make or distribute. However, you may accept compensation in exchange for copies. If you distribute a large enough number of copies you must also follow the conditions in section 3. You may also lend copies, under the same conditions stated above, and you may publicly display copies. \section{Copying in Quantity} If you publish printed copies of the Document numbering more than 100, and the Document's license notice requires Cover Texts, you must enclose the copies in covers that carry, clearly and legibly, all these Cover Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on the back cover. Both covers must also clearly and legibly identify you as the publisher of these copies. The front cover must present the full title with all words of the title equally prominent and visible. You may add other material on the covers in addition. Copying with changes limited to the covers, as long as they preserve the title of the Document and satisfy these conditions, can be treated as verbatim copying in other respects. If the required texts for either cover are too voluminous to fit legibly, you should put the first ones listed (as many as fit reasonably) on the actual cover, and continue the rest onto adjacent pages. If you publish or distribute Opaque copies of the Document numbering more than 100, you must either include a machine-readable Transparent copy along with each Opaque copy, or state in or with each Opaque copy a publicly-accessible computer-network location containing a complete Transparent copy of the Document, free of added material, which the general network-using public has access to download anonymously at no charge using public-standard network protocols. If you use the latter option, you must take reasonably prudent steps, when you begin distribution of Opaque copies in quantity, to ensure that this Transparent copy will remain thus accessible at the stated location until at least one year after the last time you distribute an Opaque copy (directly or through your agents or retailers) of that edition to the public. It is requested, but not required, that you contact the authors of the Document well before redistributing any large number of copies, to give them a chance to provide you with an updated version of the Document. \section{Modifications} You may copy and distribute a Modified Version of the Document under the conditions of sections 2 and 3 above, provided that you release the Modified Version under precisely this License, with the Modified Version filling the role of the Document, thus licensing distribution and modification of the Modified Version to whoever possesses a copy of it. In addition, you must do these things in the Modified Version: \begin{itemize} \item Use in the Title Page (and on the covers, if any) a title distinct from that of the Document, and from those of previous versions (which should, if there were any, be listed in the History section of the Document). You may use the same title as a previous version if the original publisher of that version gives permission. \item List on the Title Page, as authors, one or more persons or entities responsible for authorship of the modifications in the Modified Version, together with at least five of the principal authors of the Document (all of its principal authors, if it has less than five). \item State on the Title page the name of the publisher of the Modified Version, as the publisher. \item Preserve all the copyright notices of the Document. \item Add an appropriate copyright notice for your modifications adjacent to the other copyright notices. \item Include, immediately after the copyright notices, a license notice giving the public permission to use the Modified Version under the terms of this License, in the form shown in the Addendum below. \item Preserve in that license notice the full lists of Invariant Sections and required Cover Texts given in the Document's license notice. \item Include an unaltered copy of this License. \item Preserve the section entitled ``History'', and its title, and add to it an item stating at least the title, year, new authors, and publisher of the Modified Version as given on the Title Page. If there is no section entitled ``History'' in the Document, create one stating the title, year, authors, and publisher of the Document as given on its Title Page, then add an item describing the Modified Version as stated in the previous sentence. \item Preserve the network location, if any, given in the Document for public access to a Transparent copy of the Document, and likewise the network locations given in the Document for previous versions it was based on. These may be placed in the ``History'' section. You may omit a network location for a work that was published at least four years before the Document itself, or if the original publisher of the version it refers to gives permission. \item In any section entitled ``Acknowledgements'' or ``Dedications'', preserve the section's title, and preserve in the section all the substance and tone of each of the contributor acknowledgements and/or dedications given therein. \item Preserve all the Invariant Sections of the Document, unaltered in their text and in their titles. Section numbers or the equivalent are not considered part of the section titles. \item Delete any section entitled ``Endorsements''. Such a section may not be included in the Modified Version. \item Do not retitle any existing section as ``Endorsements'' or to conflict in title with any Invariant Section. \end{itemize} If the Modified Version includes new front-matter sections or appendices that qualify as Secondary Sections and contain no material copied from the Document, you may at your option designate some or all of these sections as invariant. To do this, add their titles to the list of Invariant Sections in the Modified Version's license notice. These titles must be distinct from any other section titles. You may add a section entitled ``Endorsements'', provided it contains nothing but endorsements of your Modified Version by various parties -- for example, statements of peer review or that the text has been approved by an organization as the authoritative definition of a standard. You may add a passage of up to five words as a Front-Cover Text, and a passage of up to 25 words as a Back-Cover Text, to the end of the list of Cover Texts in the Modified Version. Only one passage of Front-Cover Text and one of Back-Cover Text may be added by (or through arrangements made by) any one entity. If the Document already includes a cover text for the same cover, previously added by you or by arrangement made by the same entity you are acting on behalf of, you may not add another; but you may replace the old one, on explicit permission from the previous publisher that added the old one. The author(s) and publisher(s) of the Document do not by this License give permission to use their names for publicity for or to assert or imply endorsement of any Modified Version. \section{Combining Documents} You may combine the Document with other documents released under this License, under the terms defined in section 4 above for modified versions, provided that you include in the combination all of the Invariant Sections of all of the original documents, unmodified, and list them all as Invariant Sections of your combined work in its license notice. The combined work need only contain one copy of this License, and multiple identical Invariant Sections may be replaced with a single copy. If there are multiple Invariant Sections with the same name but different contents, make the title of each such section unique by adding at the end of it, in parentheses, the name of the original author or publisher of that section if known, or else a unique number. Make the same adjustment to the section titles in the list of Invariant Sections in the license notice of the combined work. In the combination, you must combine any sections entitled ``History'' in the various original documents, forming one section entitled ``History''; likewise combine any sections entitled ``Acknowledgements'', and any sections entitled ``Dedications''. You must delete all sections entitled ``Endorsements.'' \section{Collections of Documents} You may make a collection consisting of the Document and other documents released under this License, and replace the individual copies of this License in the various documents with a single copy that is included in the collection, provided that you follow the rules of this License for verbatim copying of each of the documents in all other respects. You may extract a single document from such a collection, and distribute it individually under this License, provided you insert a copy of this License into the extracted document, and follow this License in all other respects regarding verbatim copying of that document. \section{Aggregation With Independent Works} A compilation of the Document or its derivatives with other separate and independent documents or works, in or on a volume of a storage or distribution medium, does not as a whole count as a Modified Version of the Document, provided no compilation copyright is claimed for the compilation. Such a compilation is called an ``aggregate'', and this License does not apply to the other self-contained works thus compiled with the Document, on account of their being thus compiled, if they are not themselves derivative works of the Document. If the Cover Text requirement of section 3 is applicable to these copies of the Document, then if the Document is less than one quarter of the entire aggregate, the Document's Cover Texts may be placed on covers that surround only the Document within the aggregate. Otherwise they must appear on covers around the whole aggregate. \section{Translation} Translation is considered a kind of modification, so you may distribute translations of the Document under the terms of section 4. Replacing Invariant Sections with translations requires special permission from their copyright holders, but you may include translations of some or all Invariant Sections in addition to the original versions of these Invariant Sections. You may include a translation of this License provided that you also include the original English version of this License. In case of a disagreement between the translation and the original English version of this License, the original English version will prevail. \section{Termination} You may not copy, modify, sublicense, or distribute the Document except as expressly provided for under this License. Any other attempt to copy, modify, sublicense or distribute the Document is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. \section{Future Revisions of This License} The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. See http://www.gnu.org/copyleft/. Each version of the License is given a distinguishing version number. If the Document specifies that a particular numbered version of this License "or any later version" applies to it, you have the option of following the terms and conditions either of that specified version or of any later version that has been published (not as a draft) by the Free Software Foundation. If the Document does not specify a version number of this License, you may choose any version ever published (not as a draft) by the Free Software Foundation. \end{document}